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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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34 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Two-Dimensional Quantum Model of a Nanotransistor

A mathematical model, and software to implement the model, have been devised to enable numerical simulation of the transport of electric charge in, and the resulting electrical performance characteristics of, a nanotransistor [in particular, a metal oxide/semiconductor field-effect transistor (MOSFET) having a channel length of the order of tens of nanometers] in which the overall device geometry, including the doping profiles and the injection of charge from the source, gate, and drain contacts, are approximated as being two-dimensional. The model and software constitute a computational framework for quantitatively exploring such device-physics issues as those of source-drain and gate leakage currents, drain-induced barrier lowering, and threshold voltage shift due to quantization. The model and software can also be used as means of studying the accuracy of quantum corrections to other semiclassical models.

Govindan, T. R.↗
NASA NTRS1993

On-Chip p-MOSFET Dosimetry

On-chip p-FETs were developed to monitor the radiation dose of n-well CMOS ICs by monitoring the threshold voltage shifts due to radiation induced oxide and interface charge.

FET's↗
NASA NTRS1993

On-Chip p-MOSFET Dosimetry

On-chip p-FETs were developed to monitor the radiation dose of n-well CMOS ICs by monitoring threshold voltage shifts due to radiation induced oxide and interface charge.

FETs↗
NASA NTRS2001

Arc Inception Mechanism on a Solar Array Immersed in a Low-Density Plasma

In this report, results are presented of an experimental and theoretical study of arc phenomena and snapover for two samples of solar arrays immersed in argon plasma. The effects of arcing and snapover are investigated. I-V curves are measured, and arc and snapover inception voltages and arc rates are determined within the wide range of plasma parameters. A considerable increase in arc rate due to absorption of molecules from atmospheric air has been confirmed. It is shown that increasing gas pressure causes increasing ion current collection and, consequently, arc rate even though the effect of conditioning also takes place. Arc sites have been determined by employing a video-camera. It is confirmed that keeping sample under high vacuum for a long time results in shifting arc threshold voltage well below -300 V. The results obtained seem to be important for the understanding of arc inception mechanism.

Vayner, B.↗
NASA NTRS2003

Total Ionizing Dose Effects in MOS Oxides and Devices

The development of military and space electronics technology has traditionally been heavily influenced by the commercial semiconductor industry. The development of MOS technology, and particularly CMOS technology, as dominant commercial technologies has occurred entirely within the lifetime of the NSREC. For this reason, it is not surprising that the study of radiation interactions with MOS materials, devices and circuits has been a major theme of this conference for most of its history. The basic radiation problem in a MOS transistor is illustrated. The application of an appropriate gate voltage causes a conducting channel to form between the source and drain, so that current flows when the device is turned on. In Fig. lb, the effect of ionizing radiation is illustrated. Radiation-induced trapped charge has built up in the gate oxide, which causes a shift in the threshold voltage (that is, a change in the voltage which must be applied to turn the device on). If this shift is large enough, the device cannot be turned off, even at zero volts applied, and the device is said to have failed by going depletion mode.

Oldham, Timothy R.↗
NASA NTRS1994

Advanced p-MOSFET Ionizing-Radiation Dosimeter

Circuit measures total dose of ionizing radiation in terms of shift in threshold gate voltage of doped-channel metal oxide/semiconductor field-effect transistor (p-MOSFET). Drain current set at temperature-independent point to increase accuracy in determination of radiation dose.

Buehler, Martin G.↗
NASA NTRS1983

Recovery of damage in rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays

This paper reports on the recovery properties of rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays. The results indicated that complex recovery properties controlled the damage sensitivities of the tested parts. The results also indicated that damage sensitivities depended on dose rate, total dose, supply bias, gate bias, transistor type, radiation source, and particle energy. The complex nature of these dependencies make interpretation of LSI device performance in space (exposure to entire electron and proton spectra) difficult, if not impossible, without respective ground tests and analyses. Complete recovery of n-channel shifts was observed, in some cases within hours after irradiation, with equilibrium values of threshold voltages greater than their pre-irradiation values. This effect depended on total dose, radiation source, and gate bias during exposure. In contrast, the p-channel shifts recovered only 20 percent within 30 days after irradiation.

Brucker, G. J.↗
NASA NTRS1976

Shuttle spectrum despreader

The results of the spread spectrum despreader project are reported and three principal products are designed and tested. The products are, (1) a spread spectrum despreader breadboard, (2) associated test equipment consisting of a spectrum spreader and bit reconstruction/error counter and (3) paper design of a Ku-band receiver which would incorporate the despreader as a principal subsystem. The despreader and test set are designed for maximum flexibility. A choice of unbalanced quadriphase or biphase shift keyed data modulation is available. Selectable integration time and threshold voltages on the despreader further lend true usefulness as laboratory test equipment to the delivered hardware.

Source record↗
NASA NTRS1976

Effects of neutron irradiation on the characteristics of a buried channel CCD at 80 degrees Kelvin and 295 degrees Kelvin

Buried channel CCD shift registers were irradiated with 15 MeV neutrons. The irradiations were performed at 80 K and 295 K on operating devices with normal clocks and bias voltages applied. Dark current increased from the pre-irradiation value of 7 nA/sq cm to 1,600 nA/sq cm at 1 x 10 to the 13th power n/sq cm. The input gate threshold shift observed at 80K was minus 0.9 volts per 10 to the 13th power n/sq cm, a factor of 4 less than that predicted from a first order calculation of the equivalent ionization dose of neutrons in the oxide. Transfer efficiency measurements yielded a bulk electron trap creation rate for neutron irradiation of 14.0 cm to the minus 1 power at 295 K with a trap emission time constant of 25 microseconds.

Saks, N. S.↗
NASA NTRS2000

Hierarchical Statistical 3D ' Atomistic' Simulation of Decanano MOSFETs: Drift-Diffusion, Hydrodynamic and Quantum Mechanical Approaches

When MOSFETs are scaled to deep submicron dimensions the discreteness and randomness of the dopant charges in the channel region introduces significant fluctuations in the device characteristics. This effect, predicted 20 year ago, has been confirmed experimentally and in simulation studies. The impact of the fluctuations on the functionality, yield, and reliability of the corresponding systems shifts the paradigm of the numerical device simulation. It becomes insufficient to simulate only one device representing one macroscopical design in a continuous charge approximation. An ensemble of macroscopically identical but microscopically different devices has to be characterized by simulation of statistically significant samples. The aims of the numerical simulations shift from predicting the characteristics of a single device with continuous doping towards estimating the mean values and the standard deviations of basic design parameters such as threshold voltage, subthreshold slope, transconductance, drive current, etc. for the whole ensemble of 'atomistically' different devices in the system. It has to be pointed out that even the mean values obtained from 'atomistic' simulations are not identical to the values obtained from continuous doping simulations. In this paper we present a hierarchical approach to the 'atomistic' simulation of aggressively scaled decanano MOSFETs. A full scale 3D drift-diffusion'atomostic' simulation approach is first described and used for verification of the more economical, but also more restricted, options. To reduce the processor time and memory requirements at high drain voltage we have developed a self-consistent option based on a thin slab solution of the current continuity equation only in the channel region. This is coupled to the Poisson's equation solution in the whole simulation domain in the Gummel iteration cycles. The accuracy of this approach is investigated in comparison with the full self-consistent solution. At low drain voltage only single solution of the nonlinear Poisson equation is sufficient to extract the current with satisfactory accuracy. A pilot version of a hydrodynamic 'atomistic' simulator has been developed in order to study the effect of the nonequilibrium, non local transport in decanano MOSFETs on the random dopant induced current fluctuations. For the first time we have also applied the density gradient approach in 3D to investigate the effect of the quantum confinement on the threshold voltage fluctuations. The developed 'atomistic' simulation techniques have been applied to study various fluctuation resistant MOSFET architectures including epitaxial and delta doped devices.

Asenov, Asen↗
NASA NTRS1972

Shielded silicon gate complementary MOS integrated circuit.

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

Lin, H. C.↗
NASA NTRS1985

Addressable inverter matrix for process and device characterization

The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold vltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.

Buehler, M. G.↗
NASA NTRSDate not supplied

Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

We compare the failure mechanism and performance of a silicon carbide (SiC) semi-superjunction (semi-SJ) power DMOSFET against pure SJ and conventional DMOSFET when struck by a single heavy ion. The Single-Event Burnout (SEB) failure mechanism was identified as the thermal runaway from second breakdown resulting in mesoplasma formation. The semi-SJ design shifts the mesoplasma location from the drift/substrate interface seen in the control device structures to a location along the center of the P-pillar and closer towards the DMOSFET surface, thus significantly improving the SEB threshold voltage. The SEB threshold voltage varies with pillar width and ratio of pillar thickness to drift layer thickness. A maximum value of SEB threshold voltage is reached when the pillar to drift layer ratio is 0.9 and the pillar width is 2.4 μm. The semi-SJ SEB/breakdown voltage ratio is 100% and 13% higher than the pure SJ and conventional DMOSFET, respectively. Using a new figure of merit (FOM), which accounts for the tradeoff between SEB threshold voltage and on-state performance, we find that the SiC semi-SJ DMOSFET achieves a FOM that is 1.8 and 8 times higher than SJ and conventional DMOSFET, respectively, making the semi-SJ a competitive candidate for radiation hardened applications.

SiC↗
NASA NTRS1985

Addressable inverter matrix for process and device characterization

The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated in this study, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold voltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.

Buehler, M. G.↗
NASA NTRS1987

Quantification of the memory imprint effect for a charged particle environment

The effects of total accumulated dose on the single-event vulnerability of NMOS resistive-load SRAMs are investigated. The bias-dependent shifts in device parameters can imprint the memory state present during exposure or erase the imprinted state. Analysis of these effects is presented along with an analytic model developed for the quantification of these effects. The results indicate that the imprint effect is dominated by the difference in the threshold voltage of the n-channel devices.

Bhuva, B. L.↗