Strategies relating to CMP for die to wafer interconnects utilizing hybrid direct bonding.
Abstract not provided.
Mudrick, John↗
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RADIATION HARDENED ENGINEERED SUBSTRATES FOR TIME AND SPACE RESOLUTION
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Low gain avalanche detectors, wafer bonding, 3D in↗
Method of fabricating photosensitive devices with reduced process-temperature budget
A method is provided for fabricating a backside-illuminated photodetector in which a device wafer is joined to a readout wafer in an IC hybridization step. Before the IC hybridization step, the device layer is defined in the device wafer, and an LPCVD layer is formed over the device layer. The LPCVD layer may be a passivation layer, an antireflection coating, or both. The side of the device wafer having the LPCVD layer is bonded to a handle wafer, the IC is hybridized by mating the device wafer to the readout wafer, and the handle wafer is then removed, exposing the LPCVD layer. Because the LPCVD layer is formed before the active devices are fabricated, it can be made by high-temperature techniques for deposition and processing. Accordingly, a layer of high quality can be fabricated without any hazard to the active devices.
Kay, Randolph R.↗
Fine Pitch Bonding for High Density Interconnects
CTE (coefficient of thermal expansion) mismatch between two wafers has potential for brittle failure when large areas are bonded on top of one another (wafer to wafer or wafer to die bonds). To address this type of failure, we proposed patterning a polymer around metallic interconnects. For this project, utilized benzo cyclobutene (BCB) to form the bond and accommodate stress. For the metal interconnects, we used indium. To determine the benefits of utilizing BCB, mechanical shear testing of die bonding with just BCB were compared to die bonded just with oxide. These tests demonstrated that BCB, when cured for only 30 minutes and bonded at 200°C, the BCB was able to withstand shear forces similar to oxide. Furthermore, when the BCB did fail, it experienced a more ductile failure, allowing the silicon to crack, rather than shatter. To demonstrate the feasibility of using BCB between indium interconnects, wafers were pattered with layers of BCB with vias for indium or ENEPIG (electroless nickel, electroless palladium, immersion gold). Subsequently, these wafers were pattered with a variety of indium or ENEPIG interconnect pitches, diameters, and heights. These dies were bonded under a variety of conditions, and those that held a bond, were cross-sectioned and imaged. Images revealed that certain bonding conditions allow for interconnects and BCB to achieve a void-less bond and thus demonstrate that utilizing polymers in place of oxide is a feasible way to reduce CTE stress.
36 MATERIALS SCIENCE↗
Toward ultrafast, ultra-stable imaging arrays: Superlattice doping to enhance the performance of backside-illuminated 3D-hybridized silicon photodetectors
In this paper, the authors report the latest results on their development of superlattice-doped, thinned, backside-illuminated (BSI), 3D-integrated photodiode detectors—a step toward their ultimate goal of demonstrating ultrafast, ultrastable CMOS imaging arrays. As with most silicon-based photodetectors, backside-illumination and backside surface passivation are keys to achieve the highest performance capability. The two-dimensional (2D) doping technique developed at the Jet Propulsion Laboratory (JPL) has proved to result in a highly efficient, highly stable detector response when combined with a variety of detectors. Here, JPL's 2D-doping has been combined with Sandia's BSI photodetectors hybridized with custom fanout wafer via copper Direct Bond Interconnect (DBI®), a technology that is rapidly becoming industry standard for BSI CMOS imaging arrays. The prototype detectors were packaged and evaluated with respect to their response to low energy electrons. The authors find that the responsivity of 2D-doped BSI detectors is higher than devices prepared using other surface passivation techniques (i.e., ion implantation). The success of the work described herein verifies that the 2D-doping processes previously developed for Sandia's frontside-illuminated photodetectors are generally applicable to BSI detectors and demonstrates for the first time that JPL's 2D-doping process is compatible with the Cu-DBI® technology.
Jewell, April D.↗
Heterogeneous integration of an electro-optical platform
A hybrid photonic integrated circuit and a method of its manufacture are provided. A SiP functional layer is fabricated on an SOI wafer. A lithium niobate thin film is bonded to the SiP functional layer. The silicon handle layer is removed from the SOI wafer to expose buried oxide, and at least one III-V die is bonded to the exposed buried oxide. In embodiments, at least one waveguiding component is fabricated in the SiP functional layer. In embodiments, the SiP functional layer comprises a top waveguiding layer.
Kodigala, Ashok↗
Influence of Tabula Rasa on Process- and Light-Induced Degradation of Solar Cells Fabricated From Czochralski Silicon
Monocrystalline Si solar cells are fabricated from Czochralski (Cz) Si, which contains 10 17 –10 18 cm -3 oxygen atoms. Cz Si undergoes degradation during high-temperature thermal processing steps, such as dopant diffusion to form the p - n junction. This degradation in the bulk minority carrier lifetime can be related to the formation of oxygen precipitates. We found that a high-temperature annealing process known as tabula rasa (TR) not only mitigates process-induced degradation via oxygen precipitate nuclei dissolution, but also modifies subsequent light-induced degradation. We report on the bulk carrier lifetime of n - and p -type Cz Si after TR, which homogenizes the interstitial oxygen in the bulk Si to its monoatomic form in either an N 2 or O 2 environment. A control sample, which was not subjected to a TR processing step, experienced severe process-induced degradation during a boron emitter thermal budget as oxygen precipitates were formed in the Si bulk. These precipitates could be imaged using photoluminescence. Additionally, samples that underwent a TR processing step prior to the boron emitter thermal budget show efficient gettering of metallic impurities compared to the control sample, which showed a decline in the implied open-circuit voltage after the gettering step. Furthermore, modification of the interstitial oxygen bonding by TR had a strong effect on the light-induced degradation kinetics. Instead of a typically observed monotonic decrease, minority carrier lifetime increases first, followed by a nonmonotonic decrease over a ~20 h period. Finally, we conclude that by modifying the interstitial oxygen bonding via TR pretreatment, p -type Cz Si wafers become substantially resistant to harsh solar cell processes and strongly modified light-induced degradation, which would open alternative ways to mitigate this degradation mechanism.
14 SOLAR ENERGY↗
Production, quality assurance and quality control of the SiPM Tiles for the DarkSide-20k Time Projection Chamber
The DarkSide-20k dark matter direct detection experiment will employ a 21 m 2 silicon photomultiplier (SiPM) array, instrumenting a dual-phase 50 tonnes liquid argon Time Projection Chamber (TPC). SiPMs are arranged into modular photosensors called Tiles, each integrating 24 SiPMs onto a printed circuit board (PCB) that provides signal amplification, power distribution, and a single-ended output for simplified readout. Tiles are further grouped into Photo-Detector Units (PDUs). This paper details the production of the Tiles and the Quality Assurance and Quality Control (QA-QC) protocol established to ensure their performance and uniformity. The production and QA-QC of the Tiles are carried out at Nuova Officina Assergi (NOA), an ISO-6 clean room facility at LNGS. This process includes wafer-level cryogenic characterisation, precision die attaching, wire bonding, and extensive electrical and optical validation of each Tile. The overall production yield exceeds 83.5%, matching the requirements of the DarkSide-20k production plan. These results validate the robustness of the Tile design and its suitability for operation in a cryogenic environment.
Acerbi, F. [Fondazione Bruno Kessler]↗
Pulsed laser ejection of single-crystalline III-V solar cells from GaAs substrates
The best III-V solar cells start out as single-crystalline multilayers on GaAs substrates. Separating these multilayers from their growth substrate enables higher performance and wafer reuse, which are both critical for terrestrial III-V solar cell viability. Here, we remove rigidly bonded, 16 mm 2 x 3.5μm thick devices from a GaAs substrate using an unfocused Nd:YAG laser pulse. The pulse is absorbed by a low-bandgap, lattice-matched layer below the device, driving an ablation event that ejected the crystalline multilayer from the substrate. Minutes of selective wet-chemical etching and device finishing yield a 0.1 cm 2 device with a 17.4% power conversion efficiency and open-circuit voltage of 1.07 V, using AM1.5 direct with no anti-reflection coating. We show that the performance is comparable to similar cells produced via conventional processes. We discuss unique process characteristics, such as the potential to separate wafer-sized solar cells per laser pulse.
14 SOLAR ENERGY↗
Wafer-scale remote epitaxy of III-V semiconductors and applications
In conventional epitaxy of single-crystalline semiconductor materials, it is challenging to separate the grown layer with the substrate due to the strong bonding at the interface. Remote epitaxy is a recently discovered method to grow single-crystalline thin films on graphene, wherein the grown film can be exfoliated at the graphene interface to form freestanding membranes. Here, we present our recent development on remote epitaxy of III-V semiconductors. We show that directly growing 2D materials on III-V substrates as a remote epitaxy template is an ideal pathway that can eliminate transfer process-related defects and can realize wafer-scale process of remote epitaxy and substrate reuse. We present the strategies to grow 2D materials on the surface of III-V materials, which is much more challenging than thermally robust substrates such as SiO2/Si or sapphire. The nucleation of III-V on 2D material-coated III-V platforms via remote interaction is investigated both experimentally and theoretically. Lastly, we show advanced remote epitaxial platforms and optoelectronic applications enabled by remote epitaxy, and the capability to recycle the III-V substrates for repeated remote epitaxy and production of freestanding III-V thin films.
Kim, Hyunseok↗
Wafer-scale remote epitaxy of III-V semiconductors and applications
In conventional epitaxy of single-crystalline semiconductor materials, it is challenging to separate the grown layer with the substrate due to the strong bonding at the interface. Remote epitaxy is a recently discovered method to grow single-crystalline thin films on graphene, wherein the grown film can be exfoliated at the graphene interface to form freestanding membranes. Here, we present our recent development on remote epitaxy of III-V semiconductors. We show that directly growing 2D materials on III-V substrates as a remote epitaxy template is an ideal pathway that can eliminate transfer process-related defects and can realize wafer-scale process of remote epitaxy and substrate reuse. We present the strategies to grow 2D materials on the surface of III-V materials, which is much more challenging than thermally robust substrates such as SiO2/Si or sapphire. The nucleation of III-V on 2D material-coated III-V platforms via remote interaction is investigated both experimentally and theoretically. Lastly, we show advanced remote epitaxial platforms and optoelectronic applications enabled by remote epitaxy, and the capability to recycle the III-V substrates for repeated remote epitaxy and production of freestanding III-V thin films.
Kim, Hyunseok↗
Epitaxy of Beta-Ga2O3 on Highly-Offcut (Greater than 10 Degrees) Substrates
Beta-Ga2O3 has emerged as a leading candidate for next-generation power electronics, radio frequency (RF) switches, and extreme environment electronics due to a wide band gap (4.6 - 4.9 eV), high dopability (approximately 40 meV activation energy for an isolated silicon donor), and melt growth characteristics resulting in commercially available 4-inch substrates and commercial demonstrations of 6-inch substrates by multiple techniques. The (100) surface of Ga2O3 is highly desirable from a device and epitaxy standpoint - bulk growth of (100) material is more scalable than (010), the surface is nearly lattice-matched to p-type partner NiO, and Al2O3 incorporates at higher concentrations without phase separation. However, the epitaxial growth rate on (100) surfaces is less than 10% of other faces due to weak bonding and favorable desorption. Recent demonstrations have shown growth rate improvements from 0.4 nm/min to 1.5 nm/min by growing on (100) wafers that are offcut 6 degrees in the -c direction.1 These films show step-flow growth from (-201) step-edges and high electron mobility. Despite these exciting results, offcuts greater than 6 degrees have not been explored due to the waste associated with grinding and polishing large offcuts. In this talk we will discuss the molecular beam epitaxy (MBE) growth and properties of Beta-Ga2O3 grown on (100) substrates offcut in the -c direction up to 13.4 degrees. These large offcuts are enabled by edge-fed film-defined growth (EFG) where the offcut is grown into the surface by pulling the crystal through the EFG die with the seed crystal rotated by the desired offcut angle. We will demonstrate that 13.4 degrees offcut substrates still exhibit a terraced (100) surface, and that a >10x increase (4.8 nm/min) in growth rate is achieved. As previously reported on lower offcuts, we observe 100% reversal of substrate twin domains around the (001) direction at the substrate-epilayer interface. We will discuss electrical properties including record-low (by MBE) unintentional doping densities of < 5E15 cm-3.
36 MATERIALS SCIENCE↗
Silylsilane‐Substituted Polymers: Fluorine‐Free, Liquid Repellent, and Hydrolytically Stable Alternatives to Siloxanes
Abstract Per‐ and polyfluoroalkyl substances (PFAS) are omniphobic and exceptionally stable, making them ideal for a wide range of materials applications. However, as “forever chemicals”, their exceptional persistence and bioaccumulation have generated an increasing amount of environmental and health concerns, prompting the search for fluorine‐free alternatives. Siloxane‐based materials are therefore interesting to examine as PFAS alternatives due to their low surface energy and hydrophobicity but suffer from hydrolytic instability of Si─O linkages. To address this challenge, a novel methacrylate monomer, 3‐[tris(trimethylsilyl)silyl]propyl methacrylate (M‐silyl), is designed containing Si─Si bonds rather than Si─O bonds of siloxanes. Polymers derived from M‐silyl (P‐silyl) is prepared by controlled free radical polymerization and compared with their siloxane analogues after coating on silicon wafers. Contact angle (CA) measurements confirmed P‐silyl to be hydrophobic (advancing/receding water CA = 109.7°/83.0°), with a low‐hysteresis for oil (lyophobic) (hexadecane CA hysteresis = 2.0°), comparable to its siloxane‐based counterpart. Importantly, P‐silyl maintained these surface properties after exposure to acidic or basic conditions, while siloxane analogues lost hydrophobicity. Consequently, the incorporation of Si ─ Si linkages into the design of the polymer enables chemically stable, fluorine‐free alternatives for water‐repellent and low hysteresis surface coatings and advances the design of fluorine‐free functional materials.
fluorine-free↗
Thin-Entrance Window Process for Soft X-Ray Sensors
New free electron lasers, such as SLAC’s LCLS-II, will provide unique scientific imaging opportunities. In order to fully utilize these facilities, we need to develop detectors with shallow entrance windows that will enable detection of soft x-rays from 250 eV to 1.5 KeV. Achieving adequately shallow entrance windows is challenging because the high temperature anneal needed to activate the dopant also drives the dopant profile deeper, growing the region that is insensitive to soft x-rays. A new microwave annealing technology provides an efficient way to achieve shallow entrance windows in fully depleted high-resistivity silicon sensors. The microwave anneal technique can activate dopants at low substrate temperature, with minimal dopant diffusion, and can be used to fabricate both n-type and p-type entrance windows. SRP and SIMS measurements were used to verify dopant activation with negligible dopant diffusion. We then applied the microwave anneal process to a planar sensor wafer, using the new process to create the backside diode contact. Electrical test of the resulting sensors shows good reverse bias characteristics. The sensors have been bump-bonded to a read-out ASIC and used successfully to measure an Fe-55 x-ray spectrum. Process and device simulations were performed to characterize the quantum efficiency of the entrance window for soft x-rays. This technique is useful for other sensor applications requiring a shallow entrance window, including detectors for UV photons, low energy ions and low energy electrons.
47 OTHER INSTRUMENTATION↗
Room Temperature, Dip Coating Organic Passivation for c-Si Surfaces
Surface passivation of crystalline Si (c-Si) to reduce recombination rate is crucial to obtain high-efficiency c-Si solar cells. A fast passivation technique that can be performed at room temperature is needed when studying the degradation behaviors using various characterization methods to not destroy the degraded states. In this contribution, we explore Nafion via dip coating on n-type Cz wafers. We show that both the Nafion concentration and the conditions of surface and edge affect the passivation quality, and we achieve excellent passivation quality of iVoc of 716 mV, with a saturation current density (J0) of 7 fA/cm2. Additionally, electron paramagnetic resonance (EPR) shows Nafion can be used under cryogenic temperature and reveals the reduction of Si dangling bond after Nafion treatment.
dielectric solar cell↗
Fast Growth of Ga2O3 on Highly Offcut (100)-Oriented Substrates
Beta-Ga2O3 has emerged as a leading candidate for next-generation power electronics, radio frequency (RF) switches, and extreme environment electronics due to a wide band gap (4.6 - 4.9 eV), high dopability (approximately 40 meV activation energy for an isolated silicon donor), and melt growth characteristics resulting in commercially available 4-inch substrates and commercial demonstrations of 6-inch substrates by multiple techniques. The (100) surface of Ga2O3 is highly desirable from a device and epitaxy standpoint - bulk growth of (100) material is more scalable than (010), the surface is nearly lattice-matched to p-type partner NiO, and Al2O3 incorporates at higher concentrations without phase separation. More importantly, the impact ionization coefficients along the [100] direction are low, leading to the highest possible critical fields. This is advantageous compared to the current state of the art, (001), due to reduced surface defects and increased possible breakdown voltage. However, the epitaxial growth rate on (100) surfaces is less than 10% of other faces due to weak bonding and favorable desorption, and on-axis (100) growth easily forms twin domains. Recent demonstrations have shown growth rate improvements from 0.4 nm/min to 1.5 nm/min by growing on (100) wafers that are offcut 6 degrees in the -c direction. These films show step-flow growth from (20-1) step-edges and high electron mobility due to suppressed twins. Despite these exciting results, offcuts greater than 6 degrees have not been explored due to the waste associated with grinding and polishing large offcuts. In this talk we will discuss the molecular beam epitaxy (MBE) growth and properties of Beta-Ga2O3 grown on (100) substrates offcut in the -c direction up to 13.4 degrees. These large offcuts are enabled by edge-fed film-defined growth (EFG) where the offcut is grown into the surface by pulling the crystal through the EFG die with the seed crystal rotated by the desired offcut angle. We will demonstrate that 13.4 degrees offcut substrates still exhibit a terraced (100) surface, and that a >10x increase (>5 nm/min) in growth rate is achieved. As previously reported on lower offcuts, we observe reversal of substrate twin domains around the (001) direction at the substrate-epilayer interface. We will discuss electrical properties including record-low (by MBE) unintentional doping densities of < 5E15 cm-3 and critical breakdown field in Schottky barrier diodes comparable with state-of-the-art (001) Ga2O3 without edge termination.
36 MATERIALS SCIENCE↗
Micro-Transfer Printing of Repeaters on Passive Interposer
Silicon-based sensors are central to particle physics experiments and particle tracking detectors. New-generation Large Focal Plane Arrays (LFPAs) cover areas that extend beyond several square meters. Distributing power and transporting data across such areas while maintaining good signal integrity is a complicated challenge. Tiling the detector on an organic interposer would be far too expensive and take too much space while offering little to no advantage regarding signal integrity. Passive silicon interposers are much less expensive and more integrable but would worsen signal integrity because of their inherent higher dielectric constant. Active interposers are a good compromise from the economic and signal integrity standpoint; unfortunately, their yield trends to zero for areas greater than a reticle size, making this technology incompatible with our application. NHanced proposes to duplicate the behavior of a high-yield, low-cost active interposer by printing active microcomponents on a passive interposer with our die-to-wafer micro-transfer printing (MTP) technology. This resolves the signal integrity and power distribution limitations. In Phase I, we designed and simulated analog and digital repeaters to be MTPed onto a passive silicon interposer test wafer.
2.5D↗
Sulfurization as a promising surface passivation approach for both n- and p-type Si
Sulfur is shown to be an effective and promising surface passivation element for both n- and p-type Si wafers after reacting in dilute hydrogen sulfide gas (2 - 6% in argon) at 550°C. Effective minority carrier lifetimes of > 2 ms and > 0.25 ms are achieved for n- and p-type Si wafers, respectively, comparable to the industry standard thermal oxide and atomic layer deposited aluminum oxide passivation level. Surface characterization by x-ray photoelectron and emission spectroscopy reveals that sulfur is primarily bonded in a sulfide environment.
42 ENGINEERING↗