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At least 361 records · Page 20

Fully Printed High-Frequency Phased-Array Antenna on Flexible Substrate

To address the issues of flexible electronics needed for surface-to-surface, surface-to-orbit, and back-to-Earth communications necessary for manned exploration of the Moon, Mars, and beyond, a room-temperature printing process has been developed to create active, phased-array antennas (PAAs) on a flexible Kapton substrate. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proven feasible for phased-array antenna systems. The carrier mobility of an individual CNT is estimated to be at least 100,000 sq cm/V(dot)s. The CNT network in solution has carrier mobility as high as 46,770 sq cm/V(dot)s, and has a large current-density carrying capacity of approx. 1,000 mA/sq cm , which corresponds to a high carrying power of over 2,000 mW/ sq cm. Such high carrier mobility, and large current carrying capacity, allows the achievement of high-speed (>100 GHz), high-power, flexible electronic circuits that can be monolithically integrated on NASA s active phasedarray antennas for various applications, such as pressurized rovers, pressurized habitats, and spacesuits, as well as for locating beacon towers for lunar surface navigation, which will likely be performed at S-band and attached to a mobile astronaut. A fully printed 2-bit 2-element phasedarray antenna (PAA) working at 5.6 GHz, incorporating the CNT FETs as phase shifters, is demonstrated. The PAA is printed out at room temperature on 100-mm thick Kapton substrate. Four CNT FETs are printed together with microstrip time delay lines to function as a 2-bit phase shifter. The FET switch exhibits a switching speed of 0.2 ns, and works well for a 5.6-GHz RF signal. The operating frequency is measured to be 5.6 GHz, versus the state-of-the-art flexible FET operating frequency of 52 MHz. The source-drain current density is measured to be over 1,000 mA/sq cm, while the conventional organic FETs, and single carbon nanotube-based FETs, are typically in the mA to mA/sq cm range. The switching voltage used is 1.8 V, while the state-of-the-art flexible FET has a gate voltage around 50 V. The gate voltage can effectively control the source-drain current with an ON-OFF ratio of over 1,000 obtained at a low Vds bias of 1.8 V. The azimuth steering angles of PAA are measured at 0deg, -14.5deg, -30deg, and 48.6deg. The measured far-field patterns agree well with simulation results. The efficiency of the 2-bit 2-element PAA is measured to be 39 percent, including the loss of transmission line, FET switch, and coupling loss of RF probes. With further optimization, the efficiency is expected to be around 50-60 percent.

Chen, Yihong↗

High Temperature Devices for Aerospace Applications

This presentation will overview important new capabilities and benefits that next-generation higher temperature electronics promise for a variety of aerospace systems and missions. Initial aerospace infusions of higher temperature electronics to be discussed include jet engines and the prolonged robotic exploration of the Venus surface. Complete redesign of systems compared to prior conventional electronics practices would yield the most revolutionary benefits. However, the inherent higher risk and expense associated with new technology adoption will likely drive a more evolutionary technology infusion process, especially since flight qualification demands large safety margins and testing that ensures reliable operation for far longer than actual mission duration. SiC pn-junction based devices are inherently capable of the most durable operation at the highest application temperatures compared other transistor technologies, but such integrated circuits (ICs) will never achieve integration levels near today’s silicon ICs. Extreme temperature high-power devices will also be de-rated compared to room-temperature performance. While the high temperature market will always be small compared to the conventional temperature mass-market, compatibility and leveraging of existing foundry manufacturing is vital to the establishment of a sustainable high temperature electronics ecosystem sufficient to significantly improve aerospace systems.

High Temperature↗

SEM analysis of ionizing radiation effects in an analog to digital converter /AD571/

The considered investigation is concerned with the study of the total-dose degradation mechanisms in an IIL analog to digital (A/D) converter. The A/D converter is a 10 digit device having nine separate functional units on the chip which encompass several hundred transistors and circuit elements. It was the objective of the described research to find the radiation sensitive elements by a systematic search of the devices on the LSI chip. The employed technique using a scanning electron microscope to determine the functional blocks of an integrated circuit which are sensitive to ionizing radiation and then progressively zeroing in on the soft components within those blocks, proved extremely successful on the AD571. Four functional blocks were found to be sensitive to radiation, including the Voltage Reference, DAC, IIL Clock, and IIL SAR.

Gauthier, M. K.↗

Microwave and millimeter-wave resonant-tunneling devices

Resonant-tunneling devices in microelectronic component form, whose structure is the electron analog of a Fabry-Perot resonator, encompass oscillators, self-oscillating mixers, and harmonic multipliers. The negative differential resistance characteristic of these devices has been obtained at room temperature, and resonant-tunneling transistors capable of operation in the THz-frequency range appear to be feasible. Three-terminal resonant-tunneling device development is in its infancy, as is that of devices for digital applications.

Sollner, T. C. L. Gerhard↗

Alumina Based 500 C Electronic Packaging Systems and Future Development

NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

Chen, Liang-Yu↗

Total-dose radiation effects data for semiconductor devices: 1985 supplement, volume 1

Steady-state, total-dose radiation test data are provided, in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 provides total-dose radiation test data on integrated circuits. Volume 1 of this 1985 Supplement contains new total-dose radiation test data generated since the August 1, 1981 release date of the original Volume 1. Publication of Volume 2 of the 1985 Supplement will follow that of Volume 1 by approximately three months.

Martin, K. E.↗

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

JFET↗

High-temperature optically activated GaAs power switching for aircraft digital electronic control

Gallium arsenide high-temperature devices were fabricated and assembled into an optically activated pulse-width-modulated power control for a torque motor typical of the kinds used in jet engine actuators. A bipolar heterojunction phototransistor with gallium aluminum arsenide emitter/window, a gallium arsenide junction field-effect power transistor and a gallium arsenide transient protection diode were designed and fabricated. A high-temperature fiber optic/phototransistor coupling scheme was implemented. The devices assembled into the demonstrator were successfully tested at 250 C, proving the feasibility of actuator-located switching of control power using optical signals transmitted by fibers. Assessments of the efficiency and technical merits were made for extension of this high-temperature technology to local conversion of optical power to electrical power and its control at levels useful for driving actuators. Optical power sources included in the comparisons were an infrared light-emitting diode, an injection laser diode, tungsten-halogen lamps and arc lamps. Optical-to-electrical power conversion was limited to photovoltaics located at the actuator. Impedance matching of the photovoltaic array to the load was considered over the full temperature range, -55 C to 260 C. Loss of photovoltaic efficiency at higher temperatures was taken into account. Serious losses in efficiency are: (1) in the optical source and the cooling which they may require in the assumed 125 C ambient, (2) in the decreased conversion efficiency of the gallium arsenide photovoltaic at 260 C, and (3) in impedance matching. Practical systems require improvements in these areas.

Berak, J. M.↗

Differential Resonant Ring YIG Tuned Oscillator

A differential SiGe oscillator circuit uses a resonant ring-oscillator topology in order to electronically tune the oscillator over multi-octave bandwidths. The oscillator s tuning is extremely linear, because the oscillator s frequency depends on the magnetic tuning of a YIG sphere, whose resonant frequency is equal to a fundamental constant times the DC magnetic field. This extremely simple circuit topology uses two coupling loops connecting a differential pair of SiGe bipolar transistors into a feedback configuration using a YIG tuned filter creating a closed-loop ring oscillator. SiGe device technology is used for this oscillator in order to keep the transistor s 1/f noise to an absolute minimum in order to achieve minimum RF phase noise. The single-end resonant ring oscillator currently has an advantage in fewer parts, but when the oscillation frequency is greater than 16 GHz, the package s parasitic behavior couples energy to the sphere and causes holes and poor phase noise performance. This is because the coupling to the YIG is extremely low, so that the oscillator operates at near the unloaded Q. With the differential resonant ring oscillator, the oscillation currents are just in the YIG coupling mechanisms. The phase noise is even better, and the physical size can be reduced to permit monolithic microwave integrated circuit oscillators. This invention is a YIG tuned oscillator circuit making use of a differential topology to simultaneously achieve an extremely broadband electronic tuning range and ultra-low phase noise. As a natural result of its differential circuit topology, all reactive elements, such as tuning stubs, which limit tuning bandwidth by contributing excessive open loop phase shift, have been eliminated. The differential oscillator s open-loop phase shift is associated with completely non-dispersive circuit elements such as the physical angle of the coupling loops, a differential loop crossover, and the high-frequency phase shift of the n-p-n transistors. At the input of the oscillator s feedback loop is a pair of differentially connected n-p-n SiGe transistors that provides extremely high gain, and because they are bulk-effect devices, extremely low 1/f noise (leading to ultralow RF phase noise). The 1/f corner frequency for n-p-n SiGe transistors is approximately 500 Hz. The RF energy from the transistor s collector output is connected directly to the top-coupling loop (the excitation loop) of a single-sphere YIG tuned filter. A uniform magnetic field to bias the YIG must be at a right angle to any vector associated with an RF current in a coupling loop in order for the precession to interact with the RF currents.

Parrott, Ronald A.↗

Demonstration of Y1Ba2Cu3O(7-delta) and complementary metal-oxide-semiconductor device fabrication on the same sapphire substrate

We report the first fabrication of active semiconductor and high-temperature superconducting devices on the same substrate. Test structures of complementary MOS transistors were fabricated on the same sapphire substrate as test structures of Y1Ba2Cu3O(7-delta) flux-flow transistors, and separately, Y1Ba2Cu3O(7-delta) superconducting quantum interference devices utilizing both biepitaxial and step-edge Josephson junctions. Both semiconductor and superconductor devices were operated at 77 K. The cofabrication of devices using these disparate yet complementary electronic technologies on the same substrate opens the door for the fabrication of true semiconductive/superconductive hybrid integrated circuits capable of exploiting the best features of each of these technologies.

Burns, M. J.↗

2D Quantum Mechanical Study of Nanoscale MOSFETs

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. We present the results of our simulations of MIT 25, 50 and 90 nm "well-tempered" MOSFETs and compare them to those of classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. Surprisingly, the self-consistent potential profile shows lower injection barrier in the channel in quantum case. These results are qualitatively consistent with ID Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and subthreshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Svizhenko, Alexei↗

2-D Modeling of Nanoscale MOSFETs: Non-Equilibrium Green's Function Approach

We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Electron-electron interaction is treated within Hartree approximation by solving NEGF and Poisson equations self-consistently. For the calculations presented here, parallelization is performed by distributing the solution of NEGF equations to various processors, energy wise. We present simulation of the "benchmark" MIT 25nm and 90nm MOSFETs and compare our results to those from the drift-diffusion simulator and the quantum-corrected results available. In the 25nm MOSFET, the channel length is less than ten times the electron wavelength, and the electron scattering time is comparable to its transit time. Our main results are: (1) Simulated drain subthreshold current characteristics are shown, where the potential profiles are calculated self-consistently by the corresponding simulation methods. The current predicted by our quantum simulation has smaller subthreshold slope of the Vg dependence which results in higher threshold voltage. (2) When gate oxide thickness is less than 2 nm, gate oxide leakage is a primary factor which determines off-current of a MOSFET (3) Using our 2-D NEGF simulator, we found several ways to drastically decrease oxide leakage current without compromising drive current. (4) Quantum mechanically calculated electron density is much smaller than the background doping density in the poly silicon gate region near oxide interface. This creates an additional effective gate voltage. Different ways to. include this effect approximately will be discussed.

Svizhenko, Alexei↗

High Voltage EEE Parts for EMA/EHA Applications on Manned Launch Vehicles

The objective of this paper is an assessment of high voltage electronic components required for high horsepower electric thrust vector control (TVC) systems for human spaceflight launch critical application. The scope consists of creating of a database of available Grade 1 electrical, electronic and electromechanical (EEE) parts suited to this application, a qualification path for potential non-Grade 1 EEE parts that could be used in these designs, and pathfinder testing to validate aspects of the proposed qualification plan. Advances in the state of the art in high power electric power systems enable high horsepower electric actuators, such as the electromechnical actuator (EMA) and the electro-hydrostatic actuator (EHA), to be used in launch vehicle TVC systems, dramaticly reducing weight, complexity and operating costs. Designs typically use high voltage insulated gate bipolar transistors (HV-IGBT). However, no Grade 1 HV-IGBT exists and it is unlikely that market factors alone will produce such high quality parts. Furthermore, the perception of risk, the lack of qualification methodoloy, the absence of manned space flight heritage and other barriers impede the adoption of commercial grade parts onto the critical path. The method of approach is to identify high voltage electronic component types and key parameters for parts currently used in high horsepower EMA/EHA applications, to search for higher quality substitutes and custom manufacturers, to create a database for these parts, and then to explore ways to qualify these parts for use in human spaceflight launch critical application, including grossly derating and possibly treating hybrid parts as modules. This effort is ongoing, but results thus far include identification of over 60 HV-IGBT from four manufacturers, including some with a high reliability process flow. Voltage ranges for HV-IGBT have been identified, as has screening tests used to characterize HV-IGBT. BSI BS ISO 21350 Space systems Off-the-shelf item utilization, developed from Marshall Work Instruction MWI8060.1 OFF-THE-SHELF HARDWARE UTILIZATION IN FLIGHT HARDWARE DEVELOPMENTwas found to provide guidance for including commercial off-the-shelf (COTS) hardware for use in critical applications.

Griffin, Trent↗

Oxygen and carbon in silicon

The properties of the early transistors were determined by the minority-carrier lifetime, as is the silicon photovoltaic solar cell. Most of the devices on the modern integrated circuits are majority carrier devices, in part to avoid this lifetime dependence. The micro-electronics industry typically starts with wafers with a minority-carrier lifetime of 1000 micro-seconds, but during device fabrication this lifetime is reduced to beflow 1 micro-second, in spite of extraordinary cleanliness and precautions. Process-induced defects (PID) include point defects, defect complexes, line defects, and bulk precipitates. One of the aspects that needs to be better understood is the nature of minority carrier recombination at line defects and at precipitates. Some of the PIDs are known to be related to the fast-diffusers of the iron-series transition elements. One of the common techniques of dealing with these elements is intrinsic gettering by the oxygen precipitates. But even in the gettered state, there may be a residual effect on the lifetime. Oxygen is an almost ubiquitous impurity in silicon and plays an important role in both integrated circuits and solar cells. The isolated oxygen interstitial is electrically inactive, but in its various aggregated forms it has a variety of electrical activities. The agglomeration and precipitation of oxygen, including impurity gettering and the complicating role of carbon, is discussed.

Corbett, J. W.↗

Effects of transistor geometry on CCD output sensitivity

This paper discusses recent progress in the understanding of the fabrication of low noise floating diffusion output amplifiers for special purpose charge-coupled devices. Emphasis has been given to reducing the total node capacitance and increasing the output sensitivity. Measurements of noise on experimental devices has yielded noise less than 3 electrons rms at 50 kpixel data rate.

Kim, H.↗

Self-tuning bandpass filter

An electronic filter is described which simultaneously maintains a constant bandwidth and a constant center frequency gain as the input signal frequency varies, and remains self-tuning to that center frequency over a decade range. The filter utilizes a field effect transistor (FET) as a voltage variable resistance in the bandpass frequency determining circuit. The FET is responsive to a phase detector to achieve self-tuning.

Deboo, G. J.↗