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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 361 records · Page 20
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

Free-Mass and Interface Configurations of Hammering Mechanisms

A series of free-mass designs for the ultrasonic/ sonic driller/corer (USDC) has been developed to maximize the transfer of energy from the piezoelectric transducer through the horn to the bit, as well as to minimize potential jamming. A systematic development was made producing novel designs of free-mass configurations where the impact force is spread across a minimal area maximizing the impact on the bit. The designed free masses were made to operate at high temperatures (500 C) as on Venus, and they can be made to operate at extremely low temperature, too. In normal operation, the free mass bounces between the horn and the bit, impacting both repeatedly. The impact stress profile, maximum stress, contact time duration, and the required yielding stress for the materials of the free mass, bit, and horn are all affected by the contact area. A larger contact area results in lower stress in the contact region, and avoids yielding of the materials. However, before the excitation voltage is applied to the transducer, the horn, free mass, and the bit are pressed together. Larger contact area results in a stronger coupling of the bit to the horn transducer, which greatly changes the vibration characteristics of the transducer, and makes the USDC difficult to start. To obtain optimum performance, a catalog of free-mass designs is required, allowing maximum flexibility during trade-off for these conflicting contact area requirements. For this purpose, seven different designs were conceived: point contacts, circular contacts, point/circular contacts, line contacts, ring contacts, line/ring contacts, and dashed line contacts. Besides point/circular and line/ring contacts, the free mass can be designed as any of the above shapes. Depending on the ratio of the diameter to the height, and the free-mass retention method used (the cup or rod), the free mass can be configured with one or more sliding surfaces on the outside or inside diameter surface or both. Matching horn tips and free mass may also offer some utility in maximizing the stress pulse.

Bao, Xiaoqi↗
DOE OSTI2025

Q-Cluster: Quantum Error Mitigation Through Noise-Aware Unsupervised Learning

Quantum error mitigation (QEM) is critical in reducing the impact of noise in the pre-fault-tolerant era, and is expected to complement error correction in fault-tolerant quantum computing (FTQC). In this work, we propose a novel QEM approach, Q-Cluster, that uses unsupervised learning (clustering) to reshape the measured bit-string distribution. Our approach starts with a simplified bit-flip noise model. It first performs clustering on noisy measurement results, i.e., bit-strings, based on the Hamming distance. The centroid of each cluster is calculated using a qubit-wise majority vote. Next, the noisy distribution is adjusted with the clustering outcomes and the bitflip error rates using Bayesian inference. Our simulation results show that Q-Cluster can mitigate high noise rates (up to 40% per qubit) with the simple bit-flip noise model. However, real quantum computers do not fit such a simple noise model. To address the problem, we (a) apply Pauli twirling to tailor the complex noise channels to Pauli errors, and (b) employ a machine learning model, ExtraTrees regressor, to estimate an effective bit-flip error rate using a feature vector consisting of machine calibration data (gate & measurement error rates), circuit features (number of qubits, numbers of different types of gates, etc.) and the shape of the noisy distribution (entropy). Our experimental results show that our proposed Q-Cluster scheme improves the fidelity by a factor of 1.46x, on average, compared to the unmitigated output distribution, for a set of low-entropy benchmarks on five different IBM quantum machines. Our approach outperforms the state-of-art QEM approaches RZNE [28], M3 [24], Hammer [35], and QBEEP [33] by 1.26x,1.29x,1.47x, and 2.65 x, respectively.

42 ENGINEERING↗
NASA NTRS1974

Basic memory module

Construction and electrical characterization of the 4096 x 2-bit Basic Memory Module (BMM) are reported for the Space Ultrareliable Modular Computer (SUMC) program. The module uses four 2K x 1-bit N-channel FET, random access memory chips, called array chips, and two sense amplifier chips, mounted and interconnected on a ceramic substrate. Four 5% tolerance power supplies are required. At the Module, the address, chip select, and array select lines require a 0-8.5 V MOS signal level. The data output, read-strobe, and write-enable lines operate at TTl levels. Although the module is organized as 4096 x 2 bits, it can be used in a 8196 x 1-bit application with appropriate external connections. A 4096 x 1-bit organization can be obtained by depopulating chips.

Tietze, F. C.↗
NASA NTRS1979

Digital data reformatter/deserializer

A method and apparatus is presented for reformatting and de-serializing a serially-received sequence of data words, each consisting of a fixed number of binary data bits. A block of nm bits is serially fed into a shift register or serially-connected group of shift registers. In lieu of the(nm-1)th shifts, the bits are rearranged within the shift register in parallel fashion, according to a prescribed scheme. Shifting then continues, until the first bit of each data word appears in the last bit position in the shift register, at which time that data word is shifted in parallel into an output buffer stage, from which it is outputted in parallel, after a fixed delay.

Engel, A.↗
NASA NTRS1977

Minimax decoding of cyclic block codes

A minimax decoding algorithm utilizing soft bit detection of an (n,k) cyclic block code is described which will permit the correction of up to n-k bit errors interspersed at random locations throughout the block. The decoding solution consists of: (1) identifying the ordered soft bit set and, (2) finding the minimum order solution to the resulting syndrome equations where the nonzero error vector components are constrained to be a subset of the soft bit set. An efficient implementation of the decoding operation is described. In essence, this algorithm focuses the correction capability of the code on those bit positions which have the lowest a posteriori probabilities of correct detection.

Greene, E. P.↗
NASA NTRS1980

TIROS-N Cosmic Ray study

An experimental and analytical study was performed on the impact of galactic cosmic rays on the TIROS-N satellite memory in orbit. Comparisons were made of systems equipped with the Harris HMI-6508 1 x 1024 CMOS/bulk RAM and the RCA CDP-1821 1 x 1024 bit CMOS/SOS RAM. Based upon the experimental results, estimated bit error rates were determined. These were at least 8.0 bit errors/day for a 300 kilobit memory with the HMI-6508 and .014 bit errors/day with the CDF-1821. It was also estimated that the HMI-6508 latchup rate in orbit is at least two orders of magnitude less than the bit error rates; the CDP-1821 will not latchup.

Blandford, J. T., Jr.↗
NASA NTRS1986

Fast VLSI Viterbi Decoder

Fast Viterbi decoder with fully parallel, pipeline architecture implemented on two VLSI NMOS chips. Decoder used with constraint-length-7, rate-1/2, convolutional error-correcting code widely used by NASA for deepspace telemetry data. With this (7,1/2) code, bit stream contains 2 bits per original data bit, and information about 1 data bit distributed over 7 pairs of bits. Design principles of decoder also applicable to Viterbi codes of other lengths and rates.

Wang, C. C.↗
NASA NTRS1984

The Single Event Upset (SEU) response to 590 MeV protons

The presence of high-energy protons in cosmic rays, solar flares, and trapped radiation belts around Jupiter poses a threat to the Galileo project. Results of a test of 10 device types (including 1K RAM, 4-bit microP sequencer, 4-bit slice, 9-bit data register, 4-bit shift register, octal flip-flop, and 4-bit counter) exposed to 590 MeV protons at the Swiss Institute of Nuclear Research are presented to clarify the picture of SEU response to the high-energy proton environment of Jupiter. It is concluded that the data obtained should remove the concern that nuclear reaction products generated by protons external to the device can cause significant alteration in the device SEU response. The data also show only modest increases in SEU cross section as proton energies are increased up to the upper limits of energy for both the terrestrial and Jovian trapped proton belts.

Nichols, D. K.↗
NASA NTRS1986

Adaptive Quantizer for Burst Synthetic-Aperture Radar

Adaptive quantizer for burst-mode synthetic-aperture radar reduces data rate of return signal. Device, called block floating-point quantizer (BFPQ) basically analog-to-digital converter that covers wide dynamic range and discards appropriate lower order bits. BFPQ is, in effect, digital approximator with automatic gain control. Moves floatingpoint marker binary representation of signal data in accordance with perceived dynamic range. Available step sizes thus limited to multiples of underlying smallest quantization step (represented by lowest order bit). Retains only first K most significant bits of signal; (L,K) BFPQ is one that does K-bit quantization of signal originally quantized to L bits. Quantization error simply difference between actual signal level and its binary approximation. Other potential applications for BFPQ include speech compression and picture data compression.

Joo, T. H.↗
NASA NTRS1985

Research in the design of high-performance reconfigurable systems

The initial control and programming philosophies of the RELAPSE are discussed. A block diagram showing the relationship of the Arithmetic Units (composed of Stages and Bit Processors), to the Functional Units, and other components of the RELAPSE is used to guide this discussion. The latest version of the Bit Processor design is presented. Included is a detailed discussion of the Bit Processor's new scratch pad memory component. The section also clarifies the usage of the Bit Processor's processing registers, and Input/Output functions. The final design phase of the Arithmetic Unit is underway by a study of the Proposed IEEE Floating Point Standard. The decisions on conformation to this standard will be used as inputs into the finalization of the designs of the Bit Processor, Stage, and Arithmetic Units of the RELAPSE.

Slotnick, D. L.↗
NASA NTRS1989

An alternative design for a sparse distributed memory

A new design for a Sparse Distributed Memory, called the selected-coordinate design, is described. As in the original design, there are a large number of memory locations, each of which may be activated by many different addresses (binary vectors) in a very large address space. Each memory location is defined by specifying ten selected coordinates (bit positions in the address vectors) and a set of corresponding assigned values, consisting of one bit for each selected coordinate. A memory location is activated by an address if, for all ten of the locations's selected coordinates, the corresponding bits in the address vector match the respective assigned value bits, regardless of the other bits in the address vector. Some comparative memory capacity and signal-to-noise ratio estimates for the both the new and original designs are given. A few possible hardware embodiments of the new design are described.

Jaeckel, Louis A.↗
NASA NTRS1995

Circuit for high resolution decoding of multi-anode microchannel array detectors

A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.

Kasle, David B.↗
NASA NTRS1995

Fast interrupt platform for extended DOS

Extended DOS offers the unique combination of a simple operating system which allows direct assess to the interrupt tables, 32 bit protected mode access to a 4096 MByte address space, and the use of industry standard C compilers. The drawback is that fast interrupt handling requires both 32 bit and 16 bit versions of each real-time process interrupt handler to avoid mode switches on the interrupts. A set of tools has been developed which automates the process of transforming the output of a standard 32 bit C compiler to 16 bit interrupt code which directly handles the real mode interrupts. The entire process compiles one set of source code via a make file, which boosts productivity by making the management of the compile-link cycle very simple. The software components are in the form of classes written mostly in C. A foreground process written as a conventional application which can use the standard C libraries can communicate with the background real-time classes via a message passing mechanism. The platform thus enables the integration of high performance real-time processing into a conventional application framework.

Duryea, T. W.↗
NASA NTRS1995

Fast interrupt platform for extended DOS

Extended DOS offers the unique combination of a simple operating system which allows direct access to the interrupt tables, 32 bit protected mode access to 4096 MByte address space, and the use of industry standard C compilers. The drawback is that fast interrupt handling requires both 32 bit and 16 bit versions of each real-time process interrupt handler to avoid mode switches on the interrupts. A set of tools has been developed which automates the process of transforming the output of a standard 32 bit C compiler to 16 bit interrupt code which directly handles the real mode interrupts. The entire process compiles one set of source code via a make file, which boosts productivity by making the management of the compile-link cycle very simple. The software components are in the form of classes written mostly in C. A foreground process written as a conventional application which can use the standard C libraries can communicate with the background real-time classes via a message passing mechanism. The platform thus enables the integration of high performance real-time processing into a conventional application framework.

Duryea, T. W.↗
NASA NTRS2003

Characteristics of Single-Event Upsets in a Fabric Switch (ADS151)

Abstract-Two types of single event effects - bit errors and single event functional interrupts - were observed during heavy-ion testing of the AD8151 crosspoint switch. Bit errors occurred in bursts with the average number of bits in a burst being dependent on both the ion LET and on the data rate. A pulsed laser was used to identify the locations on the chip where the bit errors and single event functional interrupts occurred. Bit errors originated in the switches, drivers, and output buffers. Single event functional interrupts occurred when the laser was focused on the second rank latch containing the data specifying the state of each switch in the 33x17 matrix.

Buchner, Stephen↗
NASA NTRS1999

Ka-Band Beam Steering Reflectarray Study

A one-meter diameter, 32 GHz active microstrip reflectarray capable of electronic beam steering has been studied. The 15_500 element array consists of rnicrostrip patch antennas, microstrip phase shifters, and dc bias lines. Specifically, the study focused on the solid-state devices and dc bias layouts for scanning the beam linearly 45 from boresight using 2-bit phase shifters. Three configurations are recommended for the reflectarray with integrated 2-bit phase shifters where the total substrate and cladding mass varies from 8 kg to 14 kg. Additionally, dc power requirements for p-i-n diodes in 1-bit, 2-bit and 3-bit phase shifting circuits are approximately 19 W, 19 W, and 39 W, respectively. The dc power requirement for phase shifters using passive MESFETs is much less than 1 W.

McSpadden, James O.↗
NASA NTRS2005

Ka-Band, MEMS Switched Line Phase Shifters Implemented in Finite Ground Coplanar Waveguide

Ka-band MEMS switched line phase shifters implemented in finite ground coplanar waveguide are described in this paper. The phase shifters are constructed of single-pole double-throw (SPDT) switches with additional reference and phase offset transmission line lengths. The one- and two-bit phase shifters are fabricated on high resistivity (HR) silicon with a dielectric constant, Epsilon(sub T) = 11.7 and a substrate thickness, t = 500microns. The switching architectures integrated within the phase shifters consist of MEMS switches that are doubly anchored cantilever beam capacitive switches with additional high inductive sections (MEMS LC device). The SPDT switch is composed of a T-junction with a MEMS LC device at each output port. The one-bit phase shifter described in this paper has an insertion loss (IL) and return loss (RL) of 0.9 dB and 30 dB while the two-bit described has an IL and RL of 1.8 dB and 30 dB respectively. The one-bit phase shifter's designed offset phase is 22.5deg and actual measured phase shift is 21.8deg. The two-bit phase shifter's designed offset phase is 22.5deg, 45deg, and 67.5deg and the actual measured phase shifts are 21.4deg, 44.2deg, and 65.8deg, respectively.

Scardelletti, Maximilian C.↗
NASA NTRS2009

Hamming and Accumulator Codes Concatenated with MPSK or QAM

In a proposed coding-and-modulation scheme, a high-rate binary data stream would be processed as follows: 1. The input bit stream would be demultiplexed into multiple bit streams. 2. The multiple bit streams would be processed simultaneously into a high-rate outer Hamming code that would comprise multiple short constituent Hamming codes a distinct constituent Hamming code for each stream. 3. The streams would be interleaved. The interleaver would have a block structure that would facilitate parallelization for high-speed decoding. 4. The interleaved streams would be further processed simultaneously into an inner two-state, rate-1 accumulator code that would comprise multiple constituent accumulator codes - a distinct accumulator code for each stream. 5. The resulting bit streams would be mapped into symbols to be transmitted by use of a higher-order modulation - for example, M-ary phase-shift keying (MPSK) or quadrature amplitude modulation (QAM). The novelty of the scheme lies in the concatenation of the multiple-constituent Hamming and accumulator codes and the corresponding parallel architectures of the encoder and decoder circuitry (see figure) needed to process the multiple bit streams simultaneously. As in the cases of other parallel-processing schemes, one advantage of this scheme is that the overall data rate could be much greater than the data rate of each encoder and decoder stream and, hence, the encoder and decoder could handle data at an overall rate beyond the capability of the individual encoder and decoder circuits.

Divsalar, Dariush↗