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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS1987

In-circuit fault injector user's guide

A fault injector system, called an in-circuit injector, was designed and developed to facilitate fault injection experiments performed at NASA-Langley's Avionics Integration Research Lab (AIRLAB). The in-circuit fault injector (ICFI) allows fault injections to be performed on electronic systems without special test features, e.g., sockets. The system supports stuck-at-zero, stuck-at-one, and transient fault models. The ICFI system is interfaced to a VAX-11/750 minicomputer. An interface program has been developed in the VAX. The computer code required to access the interface program is presented. Also presented is the connection procedure to be followed to connect the ICFI system to a circuit under test and the ICFI front panel controls which allow manual control of fault injections.

Padilla, Peter A.↗

NASA NTRS1991

Monolithic integrated circuit charge amplifier and comparator for MAMA readout

Prototype ICs for the Solar Heliospheric Observatory's Multi-Anode Microchannel Array (MAMA) have been developed; these ICs' charge-amplifier and comparator components were then tested with a view to pulse response and noise performance. All model performance predictions have been exceeded. Electrostatic discharge protection has been included on all IC connections; device operation over temperature has been consistent with model predictions.

Cole, Edward H.↗

NASA NTRS2024

EdgeCortix SAKURA-I Machine-Learning, PCIe Accelerator SEE Heavy Ion Test Report

To enable autonomy in space, machine-learning and computer vision applications become invaluable for sensor processing. However, these algorithms are computationally complex and unfeasible for many embedded central processing units (CPUs) and usually require external coprocessors, such as graphics processing units (GPUs) or accelerators specific to the application, including application specific integrated circuits (ASICs). In power-constrained systems, GPUs tend to consume more power than is acceptable (>40W), so lower-power accelerators have shown promise to provide the performance needed under spacecraft constraints. For radiation engineers, developing methodologies that can properly test CPUs, GPUs, and accelerators, and enable comparisons between them remains a necessary complication to solve as the devices become more complex. The methodology in this test aims to be a start in developing a baseline single-event effect (SEE) test for client-device machine learning accelerators. This category of devices do not host their own operating system. This testing campaign is a continuation of a previous 200 MeV proton test performed in January 2024. This report covers two heavy ion tests of the SAKURA-I card: one in April 2024, and one in June 2024. Additional data was needed after the April test due to ion-range issues experienced at higher linear-energy transfers (LETs). These range issues are described in more detail in Section 8. This experiment characterizes SEEs and data error susceptibility of the EdgeCortix SAKURA-I machine-learning accelerator under heavy ions. The device was monitored for single event upsets (SEUs) and single event functional interrupts (SEFIs) at the Lawrence Berkeley National Laboratory’s 88-inch cyclotron. The SAKURA-I board accelerates machine-learning inference applications on a host computer through a PCIex16 connection. For the purposes of devising an end to end automated analysis workflow for this experiment, the YOLO-V5 and SSD300 objection-detection models, and the ResNet-50, EfficientNet, and MobileNetV2 image classification models were used as a representative suite of analytical machine-learning models.

Seth S Roffe↗

NASA NTRS1992

Autonomous power system brassboard

The Autonomous Power System (APS) brassboard is a 20 kHz power distribution system which has been developed at NASA Lewis Research Center, Cleveland, Ohio. The brassboard exists to provide a realistic hardware platform capable of testing artificially intelligent (AI) software. The brassboard's power circuit topology is based upon a Power Distribution Control Unit (PDCU), which is a subset of an advanced development 20 kHz electrical power system (EPS) testbed, originally designed for Space Station Freedom (SSF). The APS program is designed to demonstrate the application of intelligent software as a fault detection, isolation, and recovery methodology for space power systems. This report discusses both the hardware and software elements used to construct the present configuration of the brassboard. The brassboard power components are described. These include the solid-state switches (herein referred to as switchgear), transformers, sources, and loads. Closely linked to this power portion of the brassboard is the first level of embedded control. Hardware used to implement this control and its associated software is discussed. An Ada software program, developed by Lewis Research Center's Space Station Freedom Directorate for their 20 kHz testbed, is used to control the brassboard's switchgear, as well as monitor key brassboard parameters through sensors located within these switches. The Ada code is downloaded from a PC/AT, and is resident within the 8086 microprocessor-based embedded controllers. The PC/AT is also used for smart terminal emulation, capable of controlling the switchgear as well as displaying data from them. Intelligent control is provided through use of a T1 Explorer and the Autonomous Power Expert (APEX) LISP software. Real-time load scheduling is implemented through use of a 'C' program-based scheduling engine. The methods of communication between these computers and the brassboard are explored. In order to evaluate the features of both the brassboard hardware and intelligent controlling software, fault circuits have been developed and integrated as part of the brassboard. A description of these fault circuits and their function is included. The brassboard has become an extremely useful test facility, promoting artificial intelligence (AI) applications for power distribution systems. However, there are elements of the brassboard which could be enhanced, thus improving system performance. Modifications and enhancements to improve the brassboard's operation are discussed.

Merolla, Anthony↗

NASA NTRS1972

Design, processing, and testing of lsi arrays for space station

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Lile, W. R.↗

NASA NTRS2001

A Comparison of Three-Dimensional Simulations of Traveling-Wave Tube Cold-Test Characteristics Using CST MICROWAVE STUDIO and MAFIA

Previously, it was shown that MAFIA (solutions of Maxwell's equations by the Finite Integration Algorithm), a three-dimensional simulation code, can be used to produce accurate cold-test characteristics including frequency-phase dispersion, interaction impedance, and attenuation for traveling-wave tube (TWT) slow-wave structures. In an effort to improve user-friendliness and simulation time, a model was developed to compute the cold-test parameters using the electromagnetic field simulation software package CST MICROWAVE STUDIO (MWS). Cold-test parameters were calculated for several slow-wave circuits including a ferruled coupled-cavity, a folded waveguide, and a novel finned-ladder circuit using both MWS and MAFIA. Comparisons indicate that MWS provides more accurate cold-test data with significantly reduced simulation times. Both MAFIA and MWS are based on the finite integration (FI) method; however, MWS has several advantages over MAFIA. First, it has a Windows based interface for PC operation, making it very user-friendly, whereas MAFIA is UNIX based. MWS uses a new Perfect Boundary Approximation (PBA), which increases the accuracy of the simulations by avoiding stair step approximations associated with MAFIA's representation of structures. Finally, MWS includes a Visual Basic for Applications (VBA) compatible macro language that enables the simulation process to be automated and allows for the optimization of user-defined goal functions, such as interaction impedance.

Chevalier, C. T.↗

DOE OSTI2023

In-pixel AI for lossy data compression at source for X-ray detectors

Integrating neural networks for data compression directly in the Read-Out Integrated Circuits (ROICs), i.e. the pixelated front-end, would result in a significant reduction in off-chip data transfer, overcoming the I/O bottleneck. Our ROIC test chip (AI-In-Pixel-65) is designed in a 65 nm Low Power CMOS process for the readout of pixelated X-ray detectors. Each pixel consists of an analog front-end for signal processing and a 10b analog-to-digital converter operating at 100KSPS. Here, we compare two non-reconfigurable techniques, Principal Component Analysis (PCA) and an AutoEncoder (AE) as lossy data compression engines implemented within the pixelated area. The PCA algorithm achieves 50$×$ compression, adds one clock cycle latency, and results in a 21% increase in the pixel area. The AE achieves 70$×$ compression, adds 30 clock cycle latency, and results in a similar area increase.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2023

High-fidelity trapped-ion qubit operations with scalable photonic modulators

Abstract Experiments with trapped ions and neutral atoms typically employ optical modulators in order to control the phase, frequency, and amplitude of light directed to individual atoms. These elements are expensive, bulky, consume substantial power, and often rely on free-space I/O channels, all of which pose scaling challenges. To support many-ion systems like trapped-ion quantum computers or miniaturized deployable devices like clocks and sensors, these elements must ultimately be microfabricated, ideally monolithically with the trap to avoid losses associated with optical coupling between physically separate components. In this work we design, fabricate, and test an optical modulator capable of monolithic integration with a surface-electrode ion trap. These devices consist of piezo-optomechanical photonic integrated circuits configured as multi-stage Mach-Zehnder modulators that are used to control the intensity of light delivered to a single trapped ion on a separate chip. We use quantum tomography employing hundreds of multi-gate sequences to enhance the sensitivity of the fidelity to the types and magnitudes of gate errors relevant to quantum computing and better characterize the performance of the modulators, ultimately measuring single qubit gate fidelities that exceed 99.7%.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2020

Logical gates embedding in artificial spin ice

The realization and study of arrays of interacting magnetic nanoislands, such as artificial spin ices, have reached mature levels of control that allow design and demonstration of exotic, collective behaviors not seen in natural materials. Advances in the direct manipulation of their local, binary moments also suggest a use as nanopatterned, interacting memory media, for computation within a magnetic memory. Recent experimental work has demonstrated the possibility of building logic gates from clusters of interacting magnetic domains, and yet the possibility of large scale integration of such gates can prove problematic even at the theoretical level. Here we introduce theoretically complete sets of logical gates, in principle realizable in an experiment, and we study the feasibility of their integration into tree-like circuits. By evaluating the fidelity control parameter between their collective behavior and their expected logic functionality we determine conditions for integration. Also, we test our numerical results against the presence of disorder in the couplings, showing that the design gate structure is robust to small coupling perturbations, and thus possibly to small imperfections in the fabrication of the islands.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗

NASA NTRS1978

Automated tester for MOS devices

Automated system rapidly diagnoses MOS integrated circuits. Its programed electronics investigate transistor and cell characteristics to compile data needed for screening. Program can be changed rapidly to alter test procedures, test duration, and precision.

Cockrum, R. H.↗

NASA NTRS1984

Status Panel For Video Cassette Recorders

Central array of light-emitting diodes displays status of 30 video cassette recorders (VCR's) monitoring integrated testing of Space Shuttle. Remote status panel linked to VCR's by one 37-conductor cable. Transistor/ transistor logic chips in interface circuit allow LED array to function without drawing power from VCR control circuits.

Talley, G. L., Jr.↗

NASA NTRS1995

Operational characteristics of a 200 C LC parallel resonant circuit

Research efforts are currently underway at the NASA Lewis Research Center to design and demonstrate an inverter capable of operating with a baseplate temperature of 200 C. In support of this project, various electrical components including capacitors, inductors, transformers, cables, and semiconductor switches are being developed or evaluated for integration into the inverter. In this work, a parallel LC resonant circuit was constructed and evaluated under simultaneous electrical and thermal stressing. The tests were performed in the temperature range of 25 to 200 C with an applied voltage of up to 90 V, 20 kHz. The individual components were comprised of high temperature film capacitors and powder core inductors developed in-house. The circuit was characterized in terms of the component currents and case temperatures as well as frequency of resonance as a function of applied bias and temperature. The results obtained, which have indicated good functional stability up to 200 C, are presented and discussed.

Baumann, Eric D.↗

DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

Guerrero, Sasha Camila [North Central Coll.]↗

NASA NTRS1973

The NASA computer aided design and test system

A family of computer programs facilitating the design, layout, evaluation, and testing of digital electronic circuitry is described. CADAT (computer aided design and test system) is intended for use by NASA and its contractors and is aimed predominantly at providing cost effective microelectronic subsystems based on custom designed metal oxide semiconductor (MOS) large scale integrated circuits (LSIC's). CADAT software can be easily adopted by installations with a wide variety of computer hardware configurations. Its structure permits ease of update to more powerful component programs and to newly emerging LSIC technologies. The components of the CADAT system are described stressing the interaction of programs rather than detail of coding or algorithms. The CADAT system provides computer aids to derive and document the design intent, includes powerful automatic layout software, permits detailed geometry checks and performance simulation based on mask data, and furnishes test pattern sequences for hardware testing.

Gould, J. M.↗

DOE OSTI2021

Beamline Spectroscopy of Integrated Circuits With Hard X-Ray Transition Edge Sensors at the Advanced Photon Source

At Argonne National Laboratory, we are developing hard X-ray (2 to 20 keV) Transition Edge Sensor (TES) arrays for beamline science. The significantly improved energy resolution provided by superconducting detectors compared to semiconductor-based energy-dispersive detectors, but with better collection efficiency than wavelength-dispersive instruments, will enable greatly improved X-ray emission and absorption spectroscopic measurements. Additionally, a prototype instrument with 24 microwave-frequency multiplexed pixels is now in testing at the Advanced Photon Source (APS) 1-BM beamline. Initial measurements show an energy resolution ten times better (150 eV compared to < 15 eV) than the silicon-drift detectors currently available to APS beamline users, and in particular demonstrate the ability to resolve closely-spaced emission lines in samples containing multiple transition metal elements, such as integrated circuits. Comparing fluorescence spectra of integrated circuits measured with our TESs at the beamline to those measured with silicon detectors, we find emission lines and elements largely hidden (e.g. Hf alongside Cu) from a semiconductor-based detector but well resolved by a TES. This directly shows the strengths of TES-based instruments in fluorescence mapping.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2020

Circuit Modelling of the Mechanical-Motion-Rectifier for Electrical Simulation of Ocean Wave Power Take-off

As is the case with several other mechanical power takeoffs (PTOs), the mechanical-motion-rectifier (MMR) based PTO consists of components such as one-way clutches, gears, a ball screw, mechanical couplings, and a generator. Equivalent circuit models have been created in this paper to describe the dry frictions, viscous damping, and mechanical compliances in these components, so the non-ideal efficiency and nonlinear force of the PTO can be predicted in electrical simulations by integrating these sub-circuit models. The circuit model is simplified, and its parameters are categorized as dc and ac unknowns. The dc and ac tests on the PTO are performed sequentially to extract two sets of parameters through linear regression or nonlinear curve fitting. Then, the model is validated through its prediction capability over 25 test conditions on input forces, output voltages, and efficiencies, with correlation coefficients of 0.9, 0.98, and 0.981, respectively.

42 ENGINEERING↗

NASA NTRS1978

Elevation scanning laser/multi-sensor hazard detection system controller and mirror/mast speed control components

The electro-mechanical and electronic systems involved with pointing a laser beam from a roving vehicle along a desired vector are described. A rotating 8 sided mirror, driven by a phase-locked dc motor servo system, and monitored by a precision optical shaft encoder is used. This upper assembly is then rotated about an orthogonal axis to allow scanning into all 360 deg around the vehicle. This axis is also driven by a phase locked dc motor servo-system, and monitored with an optical shaft encoder. The electronics are realized in standard TTL integrated circuits with UV-erasable proms used to store desired coordinates of laser fire. Related topics such as the interface to the existing test vehicle are discussed.

Craig, J.↗