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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 379 records · Page 21
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Tool for Crimping Flexible Circuit Leads

A hand tool has been developed for crimping leads in flexible tails that are parts of some electronic circuits -- especially some sensor circuits. The tool is used to cut the tails to desired lengths and attach solder tabs to the leads. For tailoring small numbers of circuits for special applications, this hand tool is a less expensive alternative to a commercially available automated crimping tool. The crimping tool consists of an off-the-shelf hand crimping tool plus a specialized crimping insert designed specifically for the intended application.

Hulse, Aaron↗
NASA NTRS2009

Global Electric Circuit Implications of Total Current Measurements over Electrified Clouds

We determined total conduction (Wilson) currents and flash rates for 850 overflights of electrified clouds spanning regions including the Southeastern United States, the Western Atlantic Ocean, the Gulf of Mexico, Central America and adjacent oceans, Central Brazil, and the South Pacific. The overflights include storms over land and ocean, with and without lightning, and with positive and negative Wilson currents. We combined these individual storm overflight statistics with global diurnal lightning variation data from the Lightning Imaging Sensor (LIS) and Optical Transient Detector (OTD) to estimate the thunderstorm and electrified shower cloud contributions to the diurnal variation in the global electric circuit. The contributions to the global electric circuit from lightning producing clouds are estimated by taking the mean current per flash derived from the overflight data for land and ocean overflights and combining it with the global lightning rates (for land and ocean) and their diurnal variation derived from the LIS/OTD data. We estimate the contribution of non-lightning producing electrified clouds by assuming several different diurnal variations and total non-electrified storm counts to produce estimates of the total storm currents (lightning and non-lightning producing storms). The storm counts and diurnal variations are constrained so that the resultant total current diurnal variation equals the diurnal variation in the fair weather electric field (+/-15%). These assumptions, combined with the airborne and satellite data, suggest that the total mean current in the global electric circuit ranges from 2.0 to 2.7 kA, which is greater than estimates made by others using other methods.

Mach, Douglas M.↗
NASA NTRS2010

Cost Estimate for Molybdenum and Tantalum Refractory Metal Alloy Flow Circuit Concepts

The Early Flight Fission-Test Facilities (EFF-TF) team at NASA Marshall Space Flight Center (MSFC) has been tasked by the Naval Reactors Prime Contract Team (NRPCT) to provide a cost and delivery rough order of magnitude estimate for a refractory metal-based lithium (Li) flow circuit. The design is based on the stainless steel Li flow circuit that is currently being assembled for an NRPCT task underway at the EFF-TF. While geometrically the flow circuit is not representative of a final flight prototype, knowledge has been gained to quantify (time and cost) the materials, manufacturing, fabrication, assembly, and operations to produce a testable configuration. This Technical Memorandum (TM) also identifies the following key issues that need to be addressed by the fabrication process: Alloy selection and forming, cost and availability, welding, bending, machining, assembly, and instrumentation. Several candidate materials were identified by NRPCT including molybdenum (Mo) alloy (Mo-47.5 %Re), tantalum (Ta) alloys (T-111, ASTAR-811C), and niobium (Nb) alloy (Nb-1 %Zr). This TM is focused only on the Mo and Ta alloys, since they are of higher concern to the ongoing effort. The initial estimate to complete a Mo-47%Re system ready for testing is =$9,000k over a period of 30 mo. The initial estimate to complete a T-111 or ASTAR-811C system ready for testing is =$12,000k over a period of 36 mo.

Hickman, Robert R.↗
NASA NTRS2010

Method and Circuit for In-Situ Health Monitoring of Solar Cells in Space

This innovation represents a method and circuit realization of a system designed to make in-situ measurements of test solar-cell operational parameters on orbit using readily available high-temperature and high-ionizing-radiation- tolerant electronic components. This innovation enables on-orbit in-situ solar-array health monitoring and is in response to a need recognized by the U.S. Air Force for future solar arrays for unmanned spacecraft. This system can also be constructed out of commercial-grade electronics and can be embedded into terrestrial solar power system as a diagnostics instrument. This innovation represents a novel approach to I-V curve measurement that is radiation and temperature hard, consumes very few system resources, is economical, and utilizes commercially available components. The circuit will also operate at temperatures as low as 55 C and up to +225 C, allowing it to reside close to the array in direct sunlight. It uses a swept mode transistor functioning as a resistive load while utilizing the solar cells themselves as the biasing device, so the size of the instrument is small and there is no danger of over-driving the cells. Further, this innovation utilizes nearly universal spacecraft bus resources and therefore can be readily adapted to any spacecraft bus allowing for ease of retrofit, or designed into new systems without requiring the addition of infrastructure. One unique characteristic of this innovation is that it effects the measurement of I-V curves without the use of large resistor arrays or active current sources normally used to characterize cells. A single transistor is used as a variable resistive load across the cell. This multi-measurement instrument was constructed using operational amplifiers, analog switches, voltage regulators, MOSFETs, resistors, and capacitors. The operational amplifiers, analog switches, and voltage regulators are silicon-on-insulator (SOI) technology known for its hardness to the effects of ionizing radiation. The SOI components used can tolerate temperatures up to 225 C, which gives plenty of thermal headroom allowing this circuit to perhaps reside in the solar cell panel itself where temperatures can reach over 100 C.

Krasowski, Michael J.↗
NASA NTRS2010

Combined Aircraft and Satellite-Derived Storm Electric Current and Lightning Rates Measurements and Implications for the Global Electric Circuit

Using rotating vane electric field mills and Gerdien capacitors, we measured the electric field profile and conductivity during 850 overflights of electrified shower clouds and thunderstorms spanning regions including the Southeastern United States, the Western Atlantic Ocean, the Gulf of Mexico, Central America and adjacent oceans, Central Brazil, and the South Pacific. The overflights include storms over land and ocean, with and without lightning, and with positive and negative fields above the storms. The measurements were made with the NASA ER-2 and the Altus-II high altitude aircrafts. Peak electric fields, with lightning transients removed, ranged from -1.0 kV/m to 16 kV/m, with a mean value of 0.9 kV/m. The median peak field was 0.29 kV/m. Integrating our electric field and conductivity data, we determined total conduction currents and flash rates for each overpass. With knowledge of the storm location (land or ocean) and type (with or without lightning), we determine the mean currents by location and type. The mean current for ocean storms with lightning is 1.6 A while the mean current for land storms with lightning is 1.0 A. The mean current for oceanic storms without lightning (i.e., electrified shower clouds) is 0.39 A and the mean current for land storms without lightning is 0.13 A. Thus, on average, land storms with or without lightning have about half the mean current as their corresponding oceanic storm counterparts. Over three-quarters (78%) of the land storms had detectable lightning, while less than half (43%) of the oceanic storms had lightning. We did not find any significant regional or latitudinal based patterns in our total conduction currents. By combining the aircraft derived storm currents and flash rates with diurnal lightning statistics derived from the Lightning Imaging Sensor (LIS) and Optical Transient Detector (OTD) low Earth orbiting satellites, we reproduce the diurnal variation in the global electric circuit (i.e., the Carnegie curve) to within 4% for all but two short periods of time. This excellent agreement with the Carnegie curve was obtained without any tuning or adjustment of the satellite or aircraft data. Given our data and assumptions, mean contributions to the global electric circuit are 0.7 kA (ocean) and 1.1 kA (land) from lightning-producing storms, and 0.22 kA (ocean) and 0.04 (land) from electrified shower clouds, resulting in a mean total conduction current estimate for the global electric circuit of 2.0 kA. Breaking the results down into mean storm counts reveals 1100 for land storms with lightning, 530 for ocean storms without lightning, 390 for ocean storms with lightning, and 330 for land storms without lightning.

Mach, Douglas M.↗
NASA NTRS2011

Global Electric Circuit Implications of Combined Aircraft Storm Electric Current Measurements and Satellite-Based Diurnal Lightning Statistics

Using rotating vane electric field mills and Gerdien capacitors, we measured the electric field profile and conductivity during 850 overflights of thunderstorms and electrified shower clouds (ESCs) spanning regions including the Southeastern United States, the Western Atlantic Ocean, the Gulf of Mexico, Central America and adjacent oceans, Central Brazil, and the South Pacific. The overflights include storms over land and ocean, and with positive and negative fields above the storms. Over three-quarters (78%) of the land storms had detectable lightning, while less than half (43%) of the oceanic storms had lightning. Integrating our electric field and conductivity data, we determined total conduction currents and flash rates for each overpass. With knowledge of the storm location (land or ocean) and type (with or without lightning), we determine the mean currents by location and type. The mean current for ocean thunderstorms is 1.7 A while the mean current for land thunderstorms is 1.0 A. The mean current for ocean ESCs 0.41 A and the mean current for land ESCs is 0.13 A. We did not find any significant regional or latitudinal based patterns in our total conduction currents. By combining the aircraft derived storm currents and flash rates with diurnal flash rate statistics derived from the Lightning Imaging Sensor (LIS) and Optical Transient Detector (OTD) low Earth orbiting satellites, we reproduce the diurnal variation in the global electric circuit (i.e., the Carnegie curve) to within 4% for all but two short periods of time. The agreement with the Carnegie curve was obtained without any tuning or adjustment of the satellite or aircraft data. Given our data and assumptions, mean contributions to the global electric circuit are 1.1 kA (land) and 0.7 kA (ocean) from thunderstorms, and 0.22 kA (ocean) and 0.04 (land) from ESCs, resulting in a mean total conduction current estimate for the global electric circuit of 2.0 kA. Mean storm counts are 1100 for land thunderstorms, 530 for ocean ESCs, 390 for ocean thunderstorms, and 330 for land ESCs.

Mach, Douglas M.↗
NASA NTRS2011

Conformal Thin Film Packaging for SiC Sensor Circuits in Harsh Environments

In this investigation sputtered silicon carbide annealed at 300 C for one hour is used as a conformal thin film package. A RF magnetron sputterer was used to deposit 500 nm silicon carbide films on gold metal structures on alumina wafers. To determine the reliability and resistance to immersion in harsh environments, samples were submerged in gold etchant for 24 hours, in BOE for 24 hours, and in an O2 plasma etch for one hour. The adhesion strength of the thin film was measured by a pull test before and after the chemical immersion, which indicated that the film has an adhesion strength better than 10(exp 8) N/m2; this is similar to the adhesion of the gold layer to the alumina wafer. MIM capacitors are used to determine the dielectric constant, which is dependent on the SiC anneal temperature. Finally, to demonstrate that the SiC, conformal, thin film may be used to package RF circuits and sensors, an LC resonator circuit was fabricated and tested with and without the conformal SiC thin film packaging. The results indicate that the SiC coating adds no appreciable degradation to the circuits RF performance. Index Terms Sputter, silicon carbide, MIM capacitors, LC resonators, gold etchants, BOE, O2 plasma

Scardelletti, Maximilian C.↗
NASA NTRS2009

Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from -150 C to +500 C

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

Neudeck, Philip G.↗
NASA NTRS2011

Digi Island: A Serious Game for Teaching and Learning Digital Circuit Optimization

Karnaugh maps, also known as K-maps, are a tool used to optimize or simplify digital logic circuits. A K-map is a graphical display of a logic circuit. K-map optimization is essentially the process of finding a minimum number of maximal aggregations of K-map cells. with values of 1 according to a set of rules. The Digi Island is a serious game designed for aiding students to learn K-map optimization. The game takes place on an exotic island (called Digi Island) in the Pacific Ocean . The player is an adventurer to the Digi Island and will transform it into a tourist attraction by developing real estates, such as amusement parks.and hotels. The Digi Island game elegantly converts boring 1s and Os in digital circuits into usable and unusable spaces on a beautiful island and transforms K-map optimization into real estate development, an activity with which many students are familiar and also interested in. This paper discusses the design, development, and some preliminary results of the Digi Island game.

Harper, Michael↗
NASA NTRS2011

AC Read-Out Circuits for Single Pixel Characterization of TES Microcalorimeters and Bolometers

SRON is developing Frequency Domain Multiplexing (FDM) for the read-out of transition edge sensor (TES) soft x-ray microcalorimeters for the XMS instrument of the International X-ray Observatory and far-infrared bolometers for the SAFARI instrument on the Japanese mission SPICA. In FDM the TESs are AC voltage biased at frequencies from 0.5 to 6 MHz in a superconducting LC resonant circuit and the signal is read-out by low noise and high dynamic range SQUIDs amplifiers. The TES works as an amplitude modulator. We report on several AC bias experiments performed on different detectors. In particular, we discuss the results on the characterization of Goddard Space Flight Center x-ray pixels and SRON bolometers. The paper focuses on the analysis of different read-out configurations developed to optimize the noise and the impedance matching between the detectors and the SQUID amplifier. A novel feedback network electronics has been developed to keep the SQUID in flux locked loop, when coupled to superconducting high Q circuits, and to optimally tune the resonant bias circuit. The achieved detector performances are discussed in view of the instrument requirement for the two space missions.

Gottardi, L.↗
NASA NTRS2009

Improving Heat Transfer Performance of Printed Circuit Boards

This paper will explore the ability of printed circuit boards laminated with a Carbon Core Laminate to transfer heat vs. standard printed circuit boards that use only thick layers of copper. The paper will compare the differences in heat transfer performance of printed circuit boards with and without CCL.

Schatzel, Donald V.↗
NASA NTRS2008

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication and long-term 500 degrees Centigrade operation of 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs have now demonstrated thousands of hours of continuous 500 degrees Centigrade operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Electrical characterization and modeling of transistors and circuits at temperatures from 24 degrees Centigrade to 500 degrees Centigrade is also described. Desired analog and digital IC functionality spanning this temperature range was demonstrated without changing the input signals or power supply voltages.

Neudeck, Philip G.↗
NASA NTRS2016

Numerical Simulation of a Complete Low-Speed Wind Tunnel Circuit

A numerical simulation of the complete circuit of the NASA Langley 14 x 22-ft low-speed wind tunnel is described. Inside the circuit, all turning vanes are modeled as well as the five flow control vanes downstream of the 1st corner. The fan drive system is modeled using an actuator disk for the fan blades coupled with the fan nacelle. All the surfaces are modeled as viscous walls except the turning vanes, which were modeled as inviscid surfaces. NASA Langley's TetrUSS unstructured grid software was used for grid generation and flow simulation. Two turbulence models were employed in the present study, namely, the one-equation Spalart-Allmaras model and the shear stress transport (SST) model of Menter. The paper shows the flow characteristics in the circuit and compares the results with experimental data where available.

Nayani, Sudheer N.↗
NASA NTRS2017

Hybrid Direct-Current Circuit Breaker

A circuit breaking system includes a first branch including at least one solid-state snubber; a second branch coupled in parallel to the first branch and including a superconductor and a cryogenic contactor coupled in series; and a controller operatively coupled to the at least one solid-state snubber and the cryogenic contactor and programmed to, when a fault occurs in the load circuit, activate the at least one solid-state snubber for migrating flow of the electrical current from the second branch to the first branch, and, when the fault is cleared in the load circuit, activate the cryogenic contactor for migrating the flow of the electrical current from the first branch to the second branch.

Wang, Ruxi↗
NASA NTRS2017

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Silicon Carbid↗
NASA NTRS2017

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Spry, David J.↗
NASA NTRS2018

Interconnection of Semiconductor Devices in Extreme Environment Microelectronic Integrated Circuit Chips

A process of fabrication and the resulting integrated circuit device is made of patterned metal electrical interconnections between semiconductor devices residing on and forming extremely harsh environment integrated circuit chips. The process enables more complicated wide band gap semiconductor integrated circuits with more than one level of interconnect to function for prolonged time periods (over 1000 hours) at much higher temperatures (500 C).

Spry, David J.↗
NASA NTRS2021

Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment Applications

Silicon carbide (SiC) junction field effect transistor and SiC resistor (SiC JFET-R) integrated circuits(ICs) have uniquely demonstrated prolonged operation above 450 °C that promises significant operational improvements to a variety of NASA missions. However, the SiC epiwafers used to fabricate these ICs suffer from epi-growth process immaturity that imparts large and systematic spreads in JFET threshold voltages as a function of the device distance from the center on the wafer. Furthermore, the unprecedently wide range of intended application operating temperatures (in many cases over 600 °C wide) imparts as much as 5-fold change in JFET bias currents. This Technical Memorandum documents methods by which both temperature and radius associated JFET electrical parameter variances can be adequately eliminated, or even exploited in JFET-R circuit designs. Full analog circuit examples, including operational amplifiers, and SPICE simulations across experimentally documented SiC JFET parameter extremes are given to illustrate the efficacy of these methods. The reader may use the examples in this memorandum as either an end point, to get a desired analog signal conditioning design into hardware implemented in SiC JFET-R ICs, or as a basis point from which to derive further improvement.

Michael J Krasowski↗