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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 379 records · Page 21
All sourcesNASA NTRSDOE OSTI
NASA NTRS1985

Neighborhood comparison operator

Digital values in a moving window are compared by an operator having nine comparators connected to line buffers for receiving a succession of central pixels together with eight neighborhood pixels. A single bit of program control determines whether the neighborhood pixels are to be compared with the central pixel or a threshold value. The central pixel is always compared with the threshold. The omparator output plus 2 bits indicating odd-even pixel/line information about the central pixel addresses a lookup table to provide 14 bits of information, including 2 bits which control a selector to pass either the central pixel value, the other 12 bits of table information, or the bit-wise logical OR of all nine pixels through circuit that implements a very wide OR gate.

Gennery, D. B.↗
NASA NTRS1986

Performance measurements of a data link protocol

The end-to-end performance of a program implementing IEEE Std 802.2 logical link control protocol, which provides virtual circuit and datagram service and which constitutes the top sublayer of the data link layer of the reference model for Local Area Networks is studied. The measurements of relative execution times of various functions required in transferring data, over virtual circuits or as datagrams, showed that most of the program execution time is spent in a few relatively low-level functions. One of these functions performs block movement of data in memory, and two other functions provide access to various queues. Based on this result, two alternative versions of the program which move data efficiently were written and measured. In this paper the results of the study are reported and their impact on designing hardware and software systems for a network interface are discussed.

Kanakia, Hemant↗
NASA NTRS1998

A Synthesis of Fluid Dynamics and Quantum Chemistry for the Design of Nanoelectronics

In 1959, during a famous lecture entitled "There's Plenty of Room at the Bottom", Richard Feynman focused on the startling technical possibilities that would exist at the limit of miniaturization, that being atomically precise devices with dimensions in the nanometer range. A nanometer is both a convenient unit of length for medium to large sized molecules, and the root of the name of the new interdisciplinary field of "nanotechnology". Essentially, "nanoelectronics" denotes the goal of shrinking electronic devices, such as diodes and transistors, as well as integrated circuits of such devices that can perform logical operations, down to dimensions in the range of 100 nanometers. The thirty-year hiatus in the development of nanotechnology can figuratively be seen as a period of waiting for the bottom-up and atomically precise construction skills of synthetic chemistry to meet the top-down reductionist aspirations of device physics. The sub-nanometer domain of nineteenth-century classical chemistry has steadily grown, and state-of-the-art supramolecular chemistry can achieve atomic precision in non-repeating molecular assemblies of the size desired for nanotechnology. For nanoelectronics in particular, a basic understanding of the electron transport properties of molecules must also be developed. Quantum chemistry provides powerful computational methods that can accurately predict the properties of small to medium sized molecules on a desktop workstation, and those of large molecules if one has access to a supercomputer. Of the many properties of a molecule that quantum chemistry routinely predicts, the ability to carry a current is one that had not even been considered until recently. "Currently", there is a controversy over just how to define this key property. Reminiscent of the situation in high-Tc superconductivity, much of the difficulty arises from the different models that are used to simplify the complex electronic structure of real materials. A model-independent approach has been proposed, that sacrifices the plentiful molecular orbitals and Bloch functions of conventional approaches, for a single three-dimensional observable quantity, the electron momentum density Pi(sub rho). This quantity is simply the probability of any electron having momentum rho, multiplied by the total number of electrons in the system (the position of the electron is uncertain). We have explored the utility of this new approach in providing a fundamental understanding of the electron transport properties of molecules that have provi been nominated as candidates for components in the design of nanoelectronics; phenylene-ethynylene oligomers. Some of the molecular systems that have been studied are sketched below.

MacDougall, Preston J.↗
NASA NTRS2004

Digital design using selection operations

A digital integrated circuit chip is designed by identifying a logical structure to be implemented. This logical structure is represented in terms of a logical operations, at least 5% of which include selection operations. A determination is made of logic cells that correspond to an implementation of these logical operations.

Whitaker, Sterling R.↗
NASA NTRS1989

A programmable CCD driver circuit for multiphase CCD operation

A programmable CCD (charge-coupled device) driver circuit was designed to drive CCDs in multiphased modes. The purpose of the drive electronics is to operate developmental CCD imaging arrays for NASA's tiltable moderate resolution imaging spectrometer (MODIS-T). Five objectives for the driver were considered during its design: (1) the circuit drives CCD electrode voltages between 0 V and +30 V to produce reasonable potential wells, (2) the driving sequence is started with one input signal, (3) the driving sequence is started with one input signal, (4) the circuit allows programming of frame sequences required by arrays of any size, (5) it produces interfacing signals for the CCD and the DTF (detector test facility). Simulation of the driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400,000 pixels/s. Timing and packaging parameters were verified. The design uses 54 TTL (transistor-transistor logic) chips. Two versions of hardware were fabricated: wirewrap and printed circuit board. Both were verified functionally with a logic analyzer.

Ewin, Audrey J.↗
NASA NTRS1991

Canonical multi-valued input Reed-Muller trees and forms

There is recently an increased interest in logic synthesis using EXOR gates. The paper introduces the fundamental concept of Orthogonal Expansion, which generalizes the ring form of the Shannon expansion to the logic with multiple-valued (mv) inputs. Based on this concept we are able to define a family of canonical tree circuits. Such circuits can be considered for binary and multiple-valued input cases. They can be multi-level (trees and DAG's) or flattened to two-level AND-EXOR circuits. Input decoders similar to those used in Sum of Products (SOP) PLA's are used in realizations of multiple-valued input functions. In the case of the binary logic the family of flattened AND-EXOR circuits includes several forms discussed by Davio and Green. For the case of the logic with multiple-valued inputs, the family of the flattened mv AND-EXOR circuits includes three expansions known from literature and two new expansions.

Perkowski, M. A.↗
DOE OSTI2026

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗
NASA NTRS2005

Multifunctional Logic Gate Controlled by Temperature

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Stoica, Adrian↗
NASA NTRS1974

Solid state power controllers

Solid state power controllers (SSPC's) are to be considered for use as replacements of electromechanical relays and circuit breakers in future spacecraft and aircraft. They satisfy the combined function of both the relay and circuit breaker and can be remotely controlled by small signals, typically 10 mA, 5 to 28 v(dc). They have the advantage over conventional relay/circuit breaker systems in that they can be located near the utilization equipment and the primary ac or dc bus. The low level control, trip indication and status signals can be circuited by small gauge wire for control, computer interface, logic, electrical multiplexing, onboard testing, power management, and distribution purposes. This results in increased system versatility at appreciable weight saving and increased reliability. Conventional systems require the heavy gage load wiring and the control wiring to be routed from the bus to the load to other remote relay contacts, switches, sensors, etc. and to the circuit breaker located in the flight engineer's compartment for purposes of manual reset.

Gibbs, R. S.↗
NASA NTRS2004

Evolvable Hardware for Space Applications

This article surveys the research of the Evolvable Systems Group at NASA Ames Research Center. Over the past few years, our group has developed the ability to use evolutionary algorithms in a variety of NASA applications ranging from spacecraft antenna design, fault tolerance for programmable logic chips, atomic force field parameter fitting, analog circuit design, and earth observing satellite scheduling. In some of these applications, evolutionary algorithms match or improve on human performance.

Lohn, Jason↗
NASA NTRS2004

Evolvable Hardware for Space Applications

This article surveys the research of the Evolvable Systems Group at NASA Ames Research Center. Over the past few years, our group has developed the ability to use evolutionary algorithms in a variety of NASA applications ranging from spacecraft antenna design, fault tolerance for programmable logic chips, atomic force field parameter fitting, analog circuit design, and earth observing satellite scheduling. In some of these applications, evolutionary algorithms match or improve on human performance.

Lohn, Jason↗
NASA NTRS2010

Configurable Multi-Purpose Processor

Advancements in technology have allowed the miniaturization of systems used in aerospace vehicles. This technology is driven by the need for next-generation systems that provide reliable, responsive, and cost-effective range operations while providing increased capabilities such as simultaneous mission support, increased launch trajectories, improved launch, and landing opportunities, etc. Leveraging the newest technologies, the command and telemetry processor (CTP) concept provides for a compact, flexible, and integrated solution for flight command and telemetry systems and range systems. The CTP is a relatively small circuit board that serves as a processing platform for high dynamic, high vibration environments. The CTP can be reconfigured and reprogrammed, allowing it to be adapted for many different applications. The design is centered around a configurable field-programmable gate array (FPGA) device that contains numerous logic cells that can be used to implement traditional integrated circuits. The FPGA contains two PowerPC processors running the Vx-Works real-time operating system and are used to execute software programs specific to each application. The CTP was designed and developed specifically to provide telemetry functions; namely, the command processing, telemetry processing, and GPS metric tracking of a flight vehicle. However, it can be used as a general-purpose processor board to perform numerous functions implemented in either hardware or software using the FPGA s processors and/or logic cells. Functionally, the CTP was designed for range safety applications where it would ultimately become part of a vehicle s flight termination system. Consequently, the major functions of the CTP are to perform the forward link command processing, GPS metric tracking, return link telemetry data processing, error detection and correction, data encryption/ decryption, and initiate flight termination action commands. Also, the CTP had to be designed to survive and operate in a launch environment. Additionally, the CTP was designed to interface with the WFF (Wallops Flight Facility) custom-designed transceiver board which is used in the Low Cost TDRSS Transceiver (LCT2) also developed by WFF. The LCT2 s transceiver board demodulates commands received from the ground via the forward link and sends them to the CTP, where they are processed. The CTP inputs and processes data from the inertial measurement unit (IMU) and the GPS receiver board, generates status data, and then sends the data to the transceiver board where it is modulated and sent to the ground via the return link. Overall, the CTP has combined processing with the ability to interface to a GPS receiver, an IMU, and a pulse code modulation (PCM) communication link, while providing the capability to support common interfaces including Ethernet and serial interfaces boarding a relatively small-sized, lightweight package.

Valencia, J. Emilio↗
NASA NTRS1997

Logic Design Pathology and Space Flight Electronics

Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.

Katz, Richard↗
NASA NTRS2006

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Phillips, Thomas A.↗
NASA NTRS1990

Auto-programmable impulse neural circuits

Impulse neural networks use pulse trains to communicate neuron activation levels. Impulse neural circuits emulate natural neurons at a more detailed level than that typically employed by contemporary neural network implementation methods. An impulse neural circuit which realizes short term memory dynamics is presented. The operation of that circuit is then characterized in terms of pulse frequency modulated signals. Both fixed and programmable synapse circuits for realizing long term memory are also described. The implementation of a simple and useful unsupervised learning law is then presented. The implementation of a differential Hebbian learning rule for a specific mean-frequency signal interpretation is shown to have a straightforward implementation using digital combinational logic with a variation of a previously developed programmable synapse circuit. This circuit is expected to be exploited for simple and straightforward implementation of future auto-adaptive neural circuits.

Watula, D.↗
NASA NTRS2005

Multifunctional Logic Gate Controlled by Supply Voltage

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

Stoica, Adrian↗
NASA NTRS1973

On the performance of block codes

It is important to define and evaluate measures which incorporate most, if not all, of the quantities affecting the overall system reliability. For the simple types of block codes normally employed in space communication systems, the complexity of the encoder and decoder is of little consequence, since the use of integrated circuit technology allows the construction of the basic components in an inexpensive fashion. The complexity is essentially independent of the particular code-decoder used. The processing speed is generally a function of the type of logic used and the technology in the construction of the integrated circuits.

Helgert, H. J.↗