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At least 415 records · Page 23

Origins of epitaxial macro-terraces and macro-steps on GaN substrates

Localized lattice distortions in GaN substrates can serve as nucleation sites for epitaxial macro-steps and macro-terraces. These detrimental macro-scale features give rise to optically hazy homoepitaxial GaN surfaces. After nucleating, these macro-features grow laterally along the surface and coalesce, leading to significant coverage of the wafer surface. Dot-core GaN substrates consisting of a periodic array of cores were used as a defect-engineered system, where dislocations are intentionally concentrated at the cores. The high density of threading dislocations at the cores induced localized lattice distortions. Here, these distortions are associated predominantly with lattice tilt on the order of hundreds of arcsec across ~0.5 mm laterally along the wafer surface. The resulting macro-features that nucleated at these localized distorted sites were made up of macro-terraces with lengths ranging ~30–~150 μm and macro-step heights ranging ~200–~400 nm. Another source of localized distortion was threading screw dislocations or GaN nanopipes that resulted in spiral growth and hillock formation. Based on x-ray topography and optical microscopy measurements, we speculate that the coalescence of hillocks evolves into macro-terraces and macro-steps. While previous studies focused on the substrate miscut as a means to control macro-feature formation, we show that localized lattice tilt from defects is another important contributor to macro-feature formation.

36 MATERIALS SCIENCE↗

Benchmarking high performance computing architectures with CMS’ skeleton framework

Here, in 2012 CMS evaluated which underlying concurrency technology would be the best to use for its multi-threaded framework. The available technologies were evaluated on the high throughput computing systems dominating the resources in use at that time. A skeleton framework benchmarking suite that emulates the tasks performed within a CMSSW application was used to select Intel’s Thread Building Block library, based on the measured overheads in both memory and CPU on the different technologies benchmarked. In 2016 CMS will get access to high performance computing resources that use new many core architectures; machines such as Cori Phase 1&2, Theta, Mira. Because of this we have revived the 2012 benchmark to test it’s performance and conclusions on these new architectures. This talk will discuss the results of this exercise.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

Speeding up particle track reconstruction using a parallel Kalman filter algorithm

One of the most computationally difficult problems expected for the High-Luminosity Large Hadron Collider (HL-LHC) is determining the trajectory of charged particles during event reconstruction. Algorithms used at the LHC today rely on Kalman filtering, which builds physical trajectories incrementally while incorporating material effects and error estimation. Recognizing the need for faster computational throughput, we have adapted Kalman-filter-based methods for highly parallel, many-core SIMD architectures that are now prevalent in high-performance hardware. In this paper, we discuss the design and performance of the improved tracking algorithm, referred to as mkFit. A key piece of the algorithm is the Matriplex library, containing dedicated code to optimally vectorize operations on small matrices. The physics performance of the mkFit algorithm is comparable to the nominal CMS tracking algorithm when reconstructing tracks from simulated proton-proton collisions within the CMS detector. We study the scaling of the algorithm as a function of the parallel resources utilized and find large speedups both from vectorization and multi-threading. mkFit achieves a speedup of a factor of 6 compared to the nominal algorithm when run in a single-threaded application within the CMS software framework.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Local models of two-temperature accretion disc coronae – II. Ion thermal conduction and the absence of disc evaporation

We use local stratified shearing-box simulations with magnetic field-aligned thermal conduction to study an idealized model of the coupling between a cold, radiatively efficient accretion disc, and an overlying, hot, two-temperature corona. Evaporation of a cold disc by conduction from the hot corona has been proposed as a means of mediating the soft-to-hard state transitions observed in X-ray binary systems. We model the coronal plasma in our local disc patch as an MHD fluid subject to both free-streaming ion conduction and a parametrized cooling function that captures the collisional transfer of energy from hot ions to colder, rapidly cooling leptons. In all of our models, independent of the initial net vertical magnetic flux (NF) threading the disc, we find no evidence of disc evaporation. The ion heat flux into the disc is radiated away before conduction can heat the disc’s surface layers. When an initial NF is present, steady-state temperature, density, and outflow velocities in our model coronae are unaffected by conduction. Instead of facilitating disc evaporation, thermal conduction is more likely to feed the disc with plasma condensing out of the corona, particularly in flows without NF. Our work indicates that uncertainties in the amount of NF threading the disc hold far greater influence over whether or not the disc will evaporate into a radiatively inefficient accretion flow compared to thermal conduction. We speculate that a change in net flux mediates disc truncation/evaporation.

79 ASTRONOMY AND ASTROPHYSICS↗

Pure edge-dislocation half-loops in low-temperature Ga⁢N for V-defect formation

Lateral injection of carriers through semipolar crystallographic planes into c-plane QWs is one of the new frontiers in III-N light-emitting diodes (LEDs), especially for long wavelengths. Strategic use of V-defects has proven to be the most promising method for lateral injection, and creating optimal V-defect structure and density is an important research area for reducing forward voltage and increasing wall plug efficiency. Here, in this article, we present a novel method for forming V-defects in nominally unstressed low-temperature Ga⁢N through the generation of pure edge-dislocation half-loops. We present a detailed material science analysis of the loops via scattering-contrast electron microscopy. The loops have pure-edge character with Burgers vector 1/3 ⁢⟨$11\bar{2}0$⟩, and form in a sessile orientation on {$11\bar{2}0$} a-planes. The two arms of the loops are inclined such that the extra half-planes face down toward the growth substrate. The dislocation loops can be used to intentionally form V-defects through conditions of kinetically limited growth: these conditions also favor nucleation of V-defects at ∼100% of other threading dislocations in the Ga⁢N templates. Patterned sapphire substrates (PSS) are one of the most important substrates for III-N LED growth because of their superior light extraction. However, due to its low threading dislocation density, PSS have not been used extensively for V-defect LEDs. This work provides a pathway for improved control of V-defect formation and density on LEDs grown on sapphire with the goal of enabling uniform lateral injection in these V-defect engineered LEDs with low forward voltage, including PSS for high light extraction.

LEDs↗

A High-Throughput Solver for Marginalized Graph Kernels on GPU

Here, we present the design and optimization of a solver for efficient and high-throughput computation of the marginalized graph kernel on General Purpose GPUs. The graph kernel is computed using the conjugate gradient method to solve a generalized Laplacian of the tensor product between a pair of graphs. To cope with the large gap between the instruction throughput and the memory bandwidth of the GPUs, our solver forms the graph tensor product on-the-fly without storing it in memory. This is achieved by using threads in a warp cooperatively to stream the adjacency and edge label matrices of individual graphs by small square matrix blocks called tiles, which are then staged in registers and the shared memory for later reuse. Warps across a thread block can further share tiles via the shared memory to increase data reuse. We exploit the sparsity of the graphs hierarchically by storing only non-empty tiles using a coordinate format and nonzero elements within each tile using bitmaps. We propose a new partition-based reordering algorithm for aggregating nonzero elements of the graphs into fewer but denser tiles to further exploit sparsity. We carry out extensive theoretical analyses on the graph tensor product primitives for tiles of various density and evaluate their performance on synthetic and real-world datasets. Our solver delivers three to four orders of magnitude speedup over existing CPU-based solvers such as GraKeL and GraphKernels. The capability of the solver enables kernel-based learning tasks at unprecedented scales.

97 MATHEMATICS AND COMPUTING↗

Revisiting Huffman Coding: Toward Extreme Performance on Modern GPU Architectures

Today's high-performance computing (HPC) applications are producing vast volumes of data, which are challenging to store and transfer efficiently during the execution, such that data compression is becoming a critical technique to mitigate the storage burden and data movement cost. Huffman coding is arguably the most efficient Entropy coding algorithm in information theory, such that it could be found as a fundamental step in many modern compression algorithms such as DEFLATE. On the other hand, today's HPC applications are more and more relying on the accelerators such as GPU on supercomputers, while Huffman encoding suffers from low throughput on GPUs, resulting in a significant bottleneck in the entire data processing. In this paper, we propose and implement an efficient Huffman encoding approach based on modern GPU architectures, which addresses two key challenges: (1) how to parallelize the entire Huffman encoding algorithm, including codebook construction, and (2) how to fully utilize the high memory-bandwidth feature of modern GPU architectures. The detailed contribution is fourfold. (1) We develop an efficient parallel codebook construction on GPUs that scales effectively with the number of input symbols. (2) We propose a novel reduction based encoding scheme that can efficiently merge the codewords on GPUs. (3) We optimize the overall GPU performance by leveraging the state-of-the-art CUDA APIs such as Cooperative Groups. (4) We evaluate our Huffman encoder thoroughly using six real-world application datasets on two advanced GPUs and compare with our implemented multi-threaded Huffman encoder. Experiments show that our solution can improve the encoding throughput by up to 5.0x and 6.8x on NVIDIA RTX 5000 and V100, respectively, over the state-of-the-art GPU Huffman encoder, and by up to 3.3x over the multi-thread encoder on two 28-core Xeon Platinum 8280 CPUs.

Tian, Jiannan↗

Strategies for Thinning Graded Buffer Regions in Metamorphic Solar Cells and Performance Tradeoffs

Compositionally graded buffers (CGBs) have enabled the development of inverted metamorphic (IMM) multijunction solar cells that contain three or more junctions and exhibit record efficiencies. Typically, the CGB is grown thick with a constant grading rate, because this is the most straightforward way to minimize the threading dislocation density (TDD) in device active regions. The CGB growth represents a significant expense, in terms of materials consumption and capital cost, however, hampering the economic viability of metamorphic devices. This work explores strategies for thinning Ga1-xInxP CGBs from GaAs to InP while minimizing performance loss, as evaluated by the open-circuit voltage (VOC) of ~0.74 eV Ga0.47In0.53As solar cells. Using the Ga1-xInxP CGB as a model, we demonstrate that slower grading is necessary in certain regions of the grade where dislocation nucleation rates are higher. Grading must be more gradual in these regions to suppress threading dislocation density. Grading rates can be increased in non-critical areas where dislocation nucleation is lower, permitting a thinner buffer. We demonstrate the relationship between VOC and TDD, establishing tradeoffs between thickness and performance. Through careful design, we demonstrate a CGB with a 40% thickness reduction (2 im) achieved with a VOC decrease of only 6.3% (21 mV).

14 SOLAR ENERGY↗

Designing an Epitaxially-Integrated DBR for Dislocation Mitigation in Monolithic GaAsP/Si Tandem Solar Cells

This work explores epitaxially-integrated distributed Bragg reflectors (DBR) as a strategy to mitigate the impact of threading dislocations on the performance of monolithic GaAs 0.75 P 0.25 /Si tandem solar cells. The constraints present due to materials availability and the optical transmission profile of the GaAs 0.75 P 0.25 top cell require the use of an enhanced bandwidth DBR design achieved by combining two narrow-band DBR’s with different central wavelengths. Here, the impact of this DBR structure on JSC, along with the competing effects of threading dislocation density (TDD), are investigated using a robust, experimentally informed analytical model. Implementing this DBR within the GaAs 0.75 P 0.25 /Si tandem cell structure is predicted to yield a short circuit current enhancement equivalent to an ~1.8× reduction in TDD, providing a clear demonstration of its promise as a design methodology for mitigating the impact of non-negligible defect populations.

14 SOLAR ENERGY↗

Dynamic Undervolting to Improve Energy Efficiency on Multicore X86 CPUs

Chip manufacturers introduce redundancy at various levels of CPU design to guarantee correct operation, even for worst-case combinations of non-idealities in process variation and system operating conditions. This redundancy is implemented partly in the form of voltage margins. However, for a wide range of real-world execution scenarios these margins are excessive and merely translate to increased power consumption, hindering the effort towards higher-energy efficiency in both HPC and general purpose computing. Our study on the x86-64 Haswell and Skylake multicore microarchitectures reveals-wide voltage margins, which vary across different microarchitectures, different chip parts of the same microarchitecture, and across different workloads. We find that it is necessary to quantify-voltage margins using multi-threaded and multi-instance workloads, as characterization with single-threaded and single-instance workloads that do not stress the CPU to its full capacity typically identifies overly optimistic margins that lead to errors when applied in realistic program execution scenarios. In addition, we introduce, deploy and evaluate a run-time governor that dynamically reduces the supply voltage of modern multicore x86-64 CPUs. Our governor employs a model that takes as input a set of performance metrics which are directly measurable via performance monitoring counters and have high predictive value for the minimum tolerable supply voltage (V min ), to predict and apply the appropriate reduction for the workload at hand. Compared with the conventional DVFS governor, our approach in this study achieves up to 42 percent energy savings for the Skylake family and 34 percent for the Haswell family for complex, real-world applications.

97 MATHEMATICS AND COMPUTING↗

Post Irradiation Examination of Pressurized Water Reactor Stainless Steel Internal Components

Internal structural components of pressurized water reactors (PWR), such as baffle former bolts, are subjected to significant neutron irradiation and mechanical stresses at elevated temperatures during plant operation. Over the long operation of the power plant, these conditions lead to potential degradation and reduced load-carrying capacity of these bolts. To understand property degradation more fully, to confirm the results of experimental irradiation programs, and to predict operational lifetime performance of structural materials in internal components, post irradiation examination of harvested materials from operating nuclear reactors is required. In this work, two high fluence 316 stainless steel baffle former bolts were retrieved from a commercial Westinghouse two-loop downflow type PWR and then sectioned for analysis via mechanical testing and microstructural characterization. The irradiation damage fluctuated along the bolt length with damage levels from 15 to 41 displacements per atom with the bolt head receiving approximately twice the neutron damage levels as that of the bolt thread section. Mechanical testing evaluations showed extensive irradiation hardening and a sharp decrease in fracture toughness in all parts of the bolt, though with limited variation along the bolt length. Microstructural characterization using analytical scanning transmission electron microscopy and atom probe tomography showed significant radiation induced precipitation, segregation, and dislocation loop and cavity formation. However, unlike the mechanical behavior, there was considerable variation along the bolt length but opposite of what may be expected, with more precipitation and cavity formation in the bolt thread where the neutron radiation dose is less than in the bolt head where the neutron radiation dose is higher. The cause of this variation is likely due to gradients in temperature, neutron energy spectra, and gamma irradiation.

Lach, Tim↗

Structural breakdown in high power GaN-on-GaN p-n diode devices stressed to failure

The morphology of GaN-on-GaN vertical p-i-n diode devices after reverse-bias electrical stressing to breakdown has been investigated. All failed devices had irreversible structural damage, showing large surface craters that were ∼15–35 μm deep with lengthy surface cracks. Cross-sectional electron micrographs of failed devices showed substantial concentrations of threading dislocations around the cracks and near the crater surfaces. Progressive ion-milling across damaged devices revealed high densities of threading dislocations and the presence of voids beneath the surface cracks; these features were not observed in any unstressed devices. These results should serve as a useful reference for future reliability studies of vertical high-power GaN devices.

Peri, Prudhvi (ORCID:000000022338441X)↗

Composite entanglement topology and extensional rheology of symmetric ring-linear polymer blends

Extensive molecular simulations are applied to characterize the equilibrium dynamics, entanglement topology, and nonlinear extensional rheology of symmetric ring-linear polymer blends with systematically varied ring fraction ϕR. Chains with degree of entanglement Z≈14 are mixed to produce 10 well-entangled systems with ϕR varying from neat linear to neat ring melts. Z is large enough that except for very large ϕR, the rings are threaded by multiple linear chains in equilibrium. Primitive path analysis is used to visualize and quantify the structure of the composite ring-linear entanglement network. We measure the quantity of ring-linear threading and linear-linear entanglement as a function of ϕR and identify with simple arguments a ring fraction ϕR≈0.4 where the topological constraints of the composite entanglement network are maximized. These topological analyses are used to rationalize the ϕR-dependence of ring and linear chain dynamics, conformations, and rheology. Simulations of startup uniaxial elongation flows demonstrate the extensional stress overshoot observed in recent filament stretching experiments and characterize how it depends on the blend composition and entanglement topology. The overshoot is driven by an overstretching and recoil of ring polymers due to the convective unthreading of rings from linear chains.

O’Connor, Thomas C.↗

X-Ray Diffraction Analysis of Epitaxial Layers with the Properties of a Dislocation Filter

An approach to instant testing of epitaxial films with a sharp decrease in the threading dislocation density is proposed. High-resolution X-ray diffractometry, including reciprocal space mapping, has been used. The structure of GaAs/Si(001) heterosystems with low-temperature GaAs layers has been analyzed. A decrease in the density of threading dislocations in the GaAs film with the formation of a small-angle boundary has been detected.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

WIREFRAME: Supporting Data-dependent Parallelism through Dependency Graph Execution in GPUs

GPUs lack fundamental support for data-dependent parallelism and synchronization. While CUDA Dynamic Parallelism signals progress in this direction, many limitations and challenges still re-main. This paper introducesWireframe, a hardware-software solution that enables generalized support for data-dependent parallelism and synchronization. Wireframe enables applications to naturally express execution dependencies across different thread blocks through a dependency graph abstraction at run-time, which is sent to the GPU hardware at kernel launch. At run-time, the hardware enforces the dependencies specified in the dependency graph through a dependency-aware thread block scheduler. Overall, Wireframe is able to improve total execution time up to 65.20% with an average of 45.07%.

Abdolrashidi, AmirAli↗

Spherical Region Queries on Multicore Architectures

In this short paper, we report the performance of multiple thread-parallel algorithms for spherical region queries on multicore architectures motivated by a challenging data analytics application in materials science. Performances of two tree-based algorithms and a naive algorithm are compared to identify the length scales at which these approaches perform optimally. The optimal algorithm is then used to scale the driving materials science application, which is shown to deliver over 17X speedup using 32 OpenMP threads on data sets containing many millions of atoms.

Lu, Hao↗

The Minos Computing Library: Efficient Parallel Programming for Extremely Heterogeneous Systems

Hardware specialization has become the silver bullet to achieve efficient high performance, from Systems-on-Chip systems, where hardware specialization can be ``extreme'', to large-scale HPC systems. As the complexity of the systems increases, so does the complexity of programming such architectures in a portable way. This work introduces the Minos Computing Library (MCL), as system software, programming model, and programming model runtime that facilitate programming extremely heterogeneous systems. MCL supports the execution of several multi-threaded applications within the same compute node, performs asynchronous execution of application tasks, efficiently balances computation across hardware resources, and provides performance portability. We show that code developed on a personal desktop automatically scales up to fully utilize powerful workstations with 8 GPUs and down to power-efficient embedded systems. MCL provides up to 17.5x speedup over OpenCL on NVIDIA DGX-1 systems and up to 1.88x speedup on single-GPU systems. In multi-application workloads, MCL dynamically resource allocation provides up to 2.43x performance improvement over manual, static allocation of computing resources.

Gioiosa, Roberto↗

Evaluation of OpenAI Codex for HPC Parallel Programming Models Kernel Generation

We evaluate AI-assisted generative capabilities on fundamental numerical kernels in high-performance computing (HPC), including AXPY, GEMV, GEMM, SpMV, Jacobi Stencil, and CG. We test the generated kernel codes for a variety of language-supported programming models, including (1) C++ (e.g., OpenMP [including offload], OpenACC, Kokkos, SyCL, CUDA, and HIP), (2) Fortran (e.g., OpenMP [including offload] and OpenACC), (3) Python (e.g., numpy, Numba, cuPy, and pyCUDA), and (4) Julia (e.g., Threads, CUDA.jl, AMDGPU.jl, and KernelAbstractions.jl). We use the GitHub Copilot capabilities powered by the GPT-based OpenAI Codex available in Visual Studio Code as of April 2023 to generate a vast amount of implementations given simple + + prompt variants. To quantify and compare the results, we propose a proficiency metric around the initial 10 suggestions given for each prompt. Results suggest that the OpenAI Codex outputs for C++ correlate with the adoption and maturity of programming models. For example, OpenMP and CUDA score really high, whereas HIP is still lacking. We found that prompts from either a targeted language such as Fortran or the more general purpose Python can benefit from adding code keywords, while Julia prompts perform acceptably well for its mature programming models (e.g., Threads and CUDA.jl). We expect for these benchmarks to provide a point of reference for each programming model's community. Overall, understanding the convergence of large language models, AI, and HPC is crucial due to its rapidly evolving nature and how it is redefining human-computer interactions.

Godoy, William↗