Pure edge-dislocation half-loops in low-temperature Ga⁢N for V-defect formation

Abstract

Lateral injection of carriers through semipolar crystallographic planes into c-plane QWs is one of the new frontiers in III-N light-emitting diodes (LEDs), especially for long wavelengths. Strategic use of V-defects has proven to be the most promising method for lateral injection, and creating optimal V-defect structure and density is an important research area for reducing forward voltage and increasing wall plug efficiency. Here, in this article, we present a novel method for forming V-defects in nominally unstressed low-temperature Ga⁢N through the generation of pure edge-dislocation half-loops. We present a detailed material science analysis of the loops via scattering-contrast electron microscopy. The loops have pure-edge character with Burgers vector 1/3 ⁢⟨$11\bar{2}0$⟩, and form in a sessile orientation on {$11\bar{2}0$} a-planes. The two arms of the loops are inclined such that the extra half-planes face down toward the growth substrate. The dislocation loops can be used to intentionally form V-defects through conditions of kinetically limited growth: these conditions also favor nucleation of V-defects at ∼100% of other threading dislocations in the Ga⁢N templates. Patterned sapphire substrates (PSS) are one of the most important substrates for III-N LED growth because of their superior light extraction. However, due to its low threading dislocation density, PSS have not been used extensively for V-defect LEDs. This work provides a pathway for improved control of V-defect formation and density on LEDs grown on sapphire with the goal of enabling uniform lateral injection in these V-defect engineered LEDs with low forward voltage, including PSS for high light extraction.