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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 433 records · Page 24
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

Neudeck, P. G.↗
NASA NTRS2012

Coincident Observation of Lightning using Spaceborne Spectrophotometer and Ground-Level Electromagnetic Sensors

The present study aims at assessing a possible new way to reveal the properties of lightning flash, using spectrophotometric data obtained by FORMOSAT-2/ISUAL which is the first spaceborne multicolor lightning detector. The ISUAL data was analyzed in conjunction with ground ]based electromagnetic data obtained by Duke magnetic field sensors, NLDN, North Alabama Lightning Mapping Array (LMA), and Kennedy Space Center (KSC) electric field antennas. We first classified the observed events into cloud ]to ]ground (CG) and intra ]cloud (IC) lightning based on the Duke and NLDN measurements and analyzed ISUAL data to clarify their optical characteristics. It was found that the ISUAL optical waveform of CG lightning was strongly correlated with the current moment waveform, suggesting that it is possible to evaluate the electrical properties of lightning from satellite optical measurement to some extent. The ISUAL data also indicated that the color of CG lightning turned to red at the time of return stroke while the color of IC pulses remained unchanged. Furthermore, in one CG event which was simultaneously detected by ISUAL and LMA, the observed optical emissions slowly turned red as the altitude of optical source gradually decreased. All of these results indicate that the color of lightning flash depends on the source altitude and suggest that spaceborne optical measurement could be a new tool to discriminate CG and IC lightning. In the presentation, we will also show results on the comparison between the ISUAL and KSC electric field data to clarify characteristics of each lightning process such as preliminary breakdown, return stroke, and subsequent upward illumination.

Adachi, Toru↗
NASA NTRS2015

Further Research on the Electrification of Pyrocumulus Clouds

Past research on pyrocumulus electrification has demonstrated that a variety of lightning types can occur, including cloud‐to‐ground (CG) flashes, sometimes of dominant positive polarity, as well as small intra‐cloud (IC) discharges in the upper levels of the pyro‐cloud. In Colorado during summer 2012, the first combined polarimetric radar, multi‐Doppler radar, and three‐dimensional lightning mapping array (LMA) observations of lightning‐producing pyrocumulus were obtained. These observations suggested that the National Lightning Detection Network (NLDN) was not sensitive enough to detect the small IC flashes that appear to be the dominant mode of lightning in these clouds. However, after an upgrade to the network in late 2012, the NLDN began detecting some of this pyrocumulus lightning. Multiple pyrocumulus clouds documented by the University of Wisconsin for various fires in 2013 and 2014 (including over the Rim, West Fork Complex, Yarnell Hill, Hardluck, and several other incidents) are examined and reported on here. This study exploits the increased‐sensitivity NLDN as well as the new nationwide U.S. network of polarimetric Next‐generation Radars (NEXRADs). These observations document the common occurrence of a polarimetric "dirty ice" signature ‐ modest reflectivities (20‐40+ dBZ), near‐zero differential reflectivity, and reduced correlation coefficient (less than 0.9) ‐ prior to the production of lightning. This signature is indicative of a mixture of ash and ice particles in the upper levels of the pyro‐cloud (less than ‐20 C), with the ice interpreted as being necessary for pyro‐cloud electrification. Pseudo‐Geostationary Lightning Mapper (GLM) data will be produced from the 2012 LMA observations, and the ability of GLM to detect small pyrocumulus ICs will be assessed. The utility of lightning and polarimetric radar for documenting rapid wildfire growth, as well as for documenting pyrocumulus impacts on the composition of the upper troposphere/lower stratosphere (UTLS), will be discussed.

Lang, Timothy J.↗
NASA NTRS2015

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

JFET↗
NASA NTRS2015

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Microelectronics↗
NASA NTRS2016

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over approximately 1-micrometer scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Microelectronics↗
NASA NTRS2016

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

JFET↗
NASA NTRS2015

Ion Chromatography-on-a-chip for Water Quality Analysis

We report progress towards developing a Micro-Electro-Mechanical Systems (MEMS)- based ion chromatograph (IC) for crewed spacecraft water analysis. This IC-chip is an offshoot of a NASA-funded effort to produce a high performance liquid chromatograph (HPLC)-chip. This HPLC-chip system would require a desalting (i.e. ion chromatography) step. The complete HPLC instrument consists of the Jet Propulsion Labortory's (JPL's) quadrupole ion trap mass spectrometer integrated with a state-of-the-art MEMS liquid chromatograph (LC) system developed by the California Institute of Technology's (Caltech's) Micromachining Laboratory. The IC version of the chip consist of an electrolysis-based injector, a separation column, two electrolysis pumps for gradient generation, mixer, and a built-in conductivity detector. The HPLC version of the chip also includes a nanospray tip. The low instrument mass, coupled with its high analytical capabilities, makes the LC chip ideally suitable for wide range of applications such as trace contaminant, inorganic analytical science and, when coupled to a mass spectrometer, a macromolecular detection system for either crewed space exploration vehicles or robotic planetary missions.

Kidd, R. D.↗
NASA NTRS2017

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Today's launch vehicles complex electronic and avionics systems heavily utilize Field Programmable Gate Array (FPGA) integrated circuits (IC) for their superb speed and reconfiguration capabilities. Consequently, FPGAs are prevalent ICs in communication protocols such as MILSTD- 1553B and in control signal commands such as in solenoid valve actuations. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Al Hassan, Mohammad↗
NASA NTRS2017

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

Al Hassan, Mohammad↗
NASA NTRS2017

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Al Hassan, Mohammad↗
NASA NTRS2018

FPGA Reliability and Failure Rate Analysis for Launch and Space Vehicles Environments

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will demonstrate guidelines to estimate FPGA failure rates for ascent and in space operations. The guidelines will account for hardware and radiation-induced failures, as well as Bayesian updates to failure rates. The hardware contribution of the approach accounts for physical failures of the FPGA IC. The radiation portion will expand on FPGA susceptibility to different space radiation environments.

Al Hassan, Mohammad↗
NASA NTRS2020

High Temperature Electronics for Venus Surface Applications: A Summary of Recent Technical Advances

This white paper has a technical focus meant to provide background to those unfamiliar with the challenges of high temperature electronics, and an understanding of why new surface mission concepts are now viable for Venus and other applications. It describes that, for the first time, high temperature electronics have been developed to enable a paradigm change in extended duration Venus surface exploration. This white paper concentrates on the advances made in Silicon Carbide (SiC) integrated circuit (IC) electronics that have matured to a state where a simple long-life scientific probe is feasible for Venus surface operations. These electronics have been demonstrated for more than a year at 500˚C, 60 days in high-fidelity simulated Venus surface conditions chamber, and have been integrated and demonstrated with prototype long-lived scientific observation sensor technology. Continued maturation of these needed high temperature electronics and sensors is ongoing in the Long-Lived In-Situ Solar System Explorer (LLISSE) project to provide an operational system including sensor control and operation, signal processing, power management, and communications in the early part of the 2020’s. A key focus of this work includes increasing the complexity and decreasing the power consumption of the ICs which will pave the way to enhanced capabilities, such as long-duration Venus seismic measurements. Other IC development efforts include high temperature memory, terrestrial based characterization of volcanic magma, and development of a simple microprocessor. This electronics has also shown to have exceptionally high radiation tolerance, and thus have relevance for a broad range of solar system exploration. Although presently at the level of complexity of 1970-1980 silicon-based electronics, such electronics can enable breakthroughs in Venus planetary exploration akin to 1970s-launched planetary exploration successes (such as Viking and Voyager).

High temperature Electronics↗
NASA NTRS2021

Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment Applications

Silicon carbide (SiC) junction field effect transistor and SiC resistor (SiC JFET-R) integrated circuits(ICs) have uniquely demonstrated prolonged operation above 450 °C that promises significant operational improvements to a variety of NASA missions. However, the SiC epiwafers used to fabricate these ICs suffer from epi-growth process immaturity that imparts large and systematic spreads in JFET threshold voltages as a function of the device distance from the center on the wafer. Furthermore, the unprecedently wide range of intended application operating temperatures (in many cases over 600 °C wide) imparts as much as 5-fold change in JFET bias currents. This Technical Memorandum documents methods by which both temperature and radius associated JFET electrical parameter variances can be adequately eliminated, or even exploited in JFET-R circuit designs. Full analog circuit examples, including operational amplifiers, and SPICE simulations across experimentally documented SiC JFET parameter extremes are given to illustrate the efficacy of these methods. The reader may use the examples in this memorandum as either an end point, to get a desired analog signal conditioning design into hardware implemented in SiC JFET-R ICs, or as a basis point from which to derive further improvement.

Michael J Krasowski↗
NASA NTRS2021

Very-high-energy Emission from Pulsars

Air-Cherenkov telescopes have detected pulsations at energies above 50 GeV from a growing number of Fermi pulsars. These include the Crab, Vela, PSR B1706−44, and Geminga, with the first two having pulsed detections above 1 TeV. In some cases, there appears to be very-high-energy (VHE) emission that is an extension of the Fermi spectra to high energies, while in other cases, additional higher-energy spectral components that require a separate emission mechanism may be present. We present results of broadband spectral modeling using global magnetospheric fields and multiple emission mechanisms that include synchro-curvature (SC) and inverse Compton scattered (ICS) radiation from accelerated particles (primaries) and synchrotron self-Compton (SSC) emission from lower-energy pairs. Our models predict three distinct VHE components: SC from primaries whose high-energy tail can extend to 100 GeV, SSC from pairs that can extend to several TeV, and ICS from primary particles accelerated in the current sheet that scatter pair synchrotron radiation, which appears beyond 10 TeV. Our models suggest that H.E.S.S.-II and MAGIC have detected the high-energy tail of the primary SC component that produces the Fermi spectrum in Vela, Geminga, and PSR B1706−44. We argue that the ICS component peaking above 10 TeV from Vela has been seen by H.E.S.S. Detection of this emission component from the Crab and other pulsars is possible with the High Altitude Water Cherenkov Observatory and Cherenkov Telescope Array, and will directly measure the maximum particle energy in pulsars.

Alice K. Harding↗
NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗
NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗
NASA NTRS2024

Communications System Concept of Operations (ConOp) for Supporting Second Shift (SS) Operations

Wildland fires take place most often in remote areas without access to communications infrastructure. Communication during wildfire operations is crucial for safe and effective command and control of air assets, ground-based firefighters, and fire management. Without connectivity, Incident Command (IC) cannot exchange information, receive alerts or work with all parties involved in the wildfire suppression operation. Current policy directs IC to use voice radio communications, which require no prior infrastructure, to provide information needed for the command, control and safety of personnel and resources. Cellular communications are used only for logistical purposes unless no other method is available. To address some of the shortcomings of the current state of communications, the Advanced Capabilities for Emergency Response Operations (ACERO) Second Shift (SS) technical team is developing characteristics of an air-to-ground Mesh Radio System (MRS) and preparing for a future demonstration. The MRS will allow air and ground assets to automatically join a radio network without relying on existing infrastructure and exchange information critical to maintaining situation awareness and air traffic management by the onsite IC. The MRS will also give users more options for communications in addition to voice communications.

David Fuller↗