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Thermalization and criticality on an analogue–digital quantum simulator

Abstract Understanding how interacting particles approach thermal equilibrium is a major challenge of quantum simulators 1,2 . Unlocking the full potential of such systems towards this goal requires flexible initial state preparation, precise time evolution and extensive probes for final state characterization. Here we present a quantum simulator comprising 69 superconducting qubits that supports both universal quantum gates and high-fidelity analogue evolution, with performance beyond the reach of classical simulation in cross-entropy benchmarking experiments. This hybrid platform features more versatile measurement capabilities compared with analogue-only simulators, which we leverage here to reveal a coarsening-induced breakdown of Kibble–Zurek scaling predictions 3 in theXYmodel, as well as signatures of the classical Kosterlitz–Thouless phase transition 4 . Moreover, the digital gates enable precise energy control, allowing us to study the effects of the eigenstate thermalization hypothesis 5–7 in targeted parts of the eigenspectrum. We also demonstrate digital preparation of pairwise-entangled dimer states, and image the transport of energy and vorticity during subsequent thermalization in analogue evolution. These results establish the efficacy of superconducting analogue–digital quantum processors for preparing states across many-body spectra and unveiling their thermalization dynamics.

Science & Technology - Other Topics

Modular Battery Charge Controller

A new approach to masterless, distributed, digital-charge control for batteries requiring charge control has been developed and implemented. This approach is required in battery chemistries that need cell-level charge control for safety and is characterized by the use of one controller per cell, resulting in redundant sensors for critical components, such as voltage, temperature, and current. The charge controllers in a given battery interact in a masterless fashion for the purpose of cell balancing, charge control, and state-of-charge estimation. This makes the battery system invariably fault-tolerant. The solution to the single-fault failure, due to the use of a single charge controller (CC), was solved by implementing one CC per cell and linking them via an isolated communication bus [e.g., controller area network (CAN)] in a masterless fashion so that the failure of one or more CCs will not impact the remaining functional CCs. Each micro-controller-based CC digitizes the cell voltage (V(sub cell)), two cell temperatures, and the voltage across the switch (V); the latter variable is used in conjunction with V(sub cell) to estimate the bypass current for a given bypass resistor. Furthermore, CC1 digitizes the battery current (I1) and battery voltage (V(sub batt) and CC5 digitizes a second battery current (I2). As a result, redundant readings are taken for temperature, battery current, and battery voltage through the summation of the individual cell voltages given that each CC knows the voltage of the other cells. For the purpose of cell balancing, each CC periodically and independently transmits its cell voltage and stores the received cell voltage of the other cells in an array. The position in the array depends on the identifier (ID) of the transmitting CC. After eight cell voltage receptions, the array is checked to see if one or more cells did not transmit. If one or more transmissions are missing, the missing cell(s) is (are) eliminated from cell-balancing calculations. The cell-balancing algorithm is based on the error between the cell s voltage and the other cells and is categorized into four zones of operation. The algorithm is executed every second and, if cell balancing is activated, the error variable is set to a negative low value. The largest error between the cell and the other cells is found and the zone of operation determined. If the error is zero or negative, then the cell is at the lowest voltage and no balancing action is needed. If the error is less than a predetermined negative value, a Cell Bad Flag is set. If the error is positive, then cell balancing is needed, but a hysteretic zone is added to prevent the bypass circuit from triggering repeatedly near zero error. This approach keeps the cells within a predetermined voltage range.

Button, Robert

Computational Materials for Qualification and Certification (CM4QC) Strategy Document: Maturation of Computational Materials Methods for Aviation-Focused Qualification and Certification of Metal Additive Manufacturing (as an Example of Process-Intensive Materials)

Although considerable scientific and technological advances have been made in recent years in additive manufacturing (AM) processes, these advances have not translated into significant market penetration of AM parts within the aviation industry. It is broadly acknowledged that using traditional qualification and certification (Q&C) approaches for AM components is one of the most significant barriers to broader adoption of AM, resulting in high costs, long product development and certification timelines, and complex design iterations during the product development cycle. A new approach is urgently needed. This document lays out a vision for a new Q&C paradigm with increased use of computational materials (CM) methods aimed at decreasing the time and cost of Q&C of process-intensive material (PIM) approaches in the aviation industry, with AM as the immediate use case. This vision was developed with substantial input from industry, regulatory agencies, government research organizations, and academia.

Edward H Glaessgen