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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 451 records · Page 25
All sourcesNASA NTRSDOE OSTI
NASA NTRS2017

Analyzing System on A Chip Single Event Upset Responses using Single Event Upset Data, Classical Reliability Models, and Space Environment Data

We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data. We expect to relate SEU behavior to system performance requirements. Our proposed methodology will provide better prediction of SEU responses in harsh radiation environments with confidence metrics. single event upset (SEU), single event effect (SEE), field programmable gate array devises (FPGAs)

single event effect (SEE)↗
NASA NTRS2018

Stereo Imaging Miniature Endoscope with Single Imaging Chip and Conjugated Multi-Bandpass Filters

A dual objective endoscope for insertion into a cavity of a body for providing a stereoscopic image of a region of interest inside of the body including an imaging device at the distal end for obtaining optical images of the region of interest (ROI), and processing the optical images for forming video signals for wired and/or wireless transmission and display of 3D images on a rendering device. The imaging device includes a focal plane detector array (FPA) for obtaining the optical images of the ROI, and processing circuits behind the FPA. The processing circuits convert the optical images into the video signals. The imaging device includes right and left pupil for receiving a right and left images through a right and left conjugated multi-band pass filters. Illuminators illuminate the ROI through a multi-band pass filter having three right and three left pass bands that are matched to the right and left conjugated multi-band pass filters. A full color image is collected after three or six sequential illuminations with the red, green and blue lights.

Shahinian, Hrayr Karnig↗
NASA NTRS2019

Cracking Problems in Low-Voltage Chip Ceramic Capacitors

Cracking remains the major reason of failures in multilayer ceramic capacitors (MLCCs) used in in space electronics. Due to a tight quality control of space-grade components, the probability that as manufactured capacitors have cracks is relatively low, and cracking is often occurs during assembly, handling and the following testing of the systems. Majority of capacitors with cracks are revealed during the integration and testing period, but although extremely rarely, defective parts remain undetected and result in failures during the mission. This situation is aggravated by manual soldering and rework that are often used during low volume production of circuit boards for space. Although failures of MLCCs are often attributed to the post-manufacturing stresses, in many cases they are due to a combination of certain deviations in the manufacturing processes that result in hidden defects in the parts and excessive stresses during assembly and use. This report gives an overview of design, manufacturing and testing processes of MLCCs focusing on elements related to cracking problems. The existing and new screening and qualification procedures and techniques are briefly described and assessed by their effectiveness in revealing cracks. The capability of different test methods to simulate stresses resulting in cracking, mechanisms of failures in capacitors with cracks, and possible methods of selecting the most robust to manual soldering stresses capacitors are discussed.

testing↗
NASA NTRS2017

Hybrid CMOS System-on-Chip / InP MMIC Systems for Deep-Space Planetary Exploration at mm-Wave and THz

This paper discusses the applicability of hybrid CMOS/InP-MMIC mm-Wave systems to remote sensing instrumentation for space exploration in Earth and Planetary science. We review the need for lower power and lighter weight instruments to accommodate the limited payload resources of exploration spacecraft, and then demonstrate how hybrid systems can address these challenges. An example hybrid CMOS-InP radiometer operating at 100 GHz is discoursed in detail including circuit & system design, interfacing and packaging techniques. Measurements are presented showing that the hybrid approach does not compromise instrument sensitivity.

Tang, Adrian↗
NASA NTRS2000

A Single-Chip Programmable Digital CMOS Imager with Enhanced Low Light Detection Capability

Low-power, low-cost, miniature and integrated digital imaging systems are expected to be widely used in consumer electronics in the near future. While CMOS technology has been responsible for the phenomenal growth in consumer electronics, micro-porcessors, memory, audio systems, and radio-frequency circuits (e.g. cellular phones), till recently, the video technology remained outside this mainstream.

digital↗
NASA NTRS1999

ELIPS: Toward a Sensor Fusion Processor on a Chip

The paper presents the concept and initial tests from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) processor is developed to seamlessly combine rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor in compact low power VLSI.

sensor↗
NASA NTRS1997

Surface Plasmon Tunable Filter and Spectrometer-on-a-Chip

Surface plasmon tunable filter (SPTF) is a new technology invented in Jet Propulsion Lab. When a white light is incident on a metal/air/metal structure, in certain condition, surface plasmon waves can be excited at one metal/air material interface; those photons in surface plasmon resonances wavelength range will be converted into the energy of free electrons in the metal than coupled into the other metal film, and re-radiate out the color light.

Surface↗