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NASA Electronic Parts and Packaging (NEPP) is developing a process to be employed in critical applications. The framework assesses levels of trust and assurance in microelectronic systems. The process is being created with participation from a variety of organizations. We present a synopsis of the framework that includes contributions from The Aerospace Corporation.
Copper wire bond technology developments continue to be a subject of technical interest to the NASA (National Aeronautics and Space Administration) NEPP (NASA Electronic Parts and Packaging Program) which funded this update. Based on this new research, additional copper bond wire vulnerabilities were found in the literature - Crevice corrosion, intrinsic degradation of palladium coated copper wire, congregation of palladium near ball bond interface leading to failure, residual aluminum pad metallization impact on device lifetimes, stitch cracking phenomena, package delamination's that have resulted in wire bond failures and device failure due to elemental sulfur. A search of the U.S.A. patent web site found 3 noteworthy patents on the following developments: claim of a certain IMC (Intermetallic Compound) thickness as a mitigation solution to chlorine corrosion; claim of using materials with different pHs to neutralize contaminants in a package containing copper wire bonds; and a discussion on ball shear test threshold values for different applications. In addition, an aerospace contractor of military hardware had a presentation on copper bond wires where it was reported that there was a parametric shift and noise susceptibility of devices with copper bond wires which affected legacy design performance. A review of silver bond wire (another emerging technology) technical papers found that an electromigration failure mechanism was evident in device applications that operate under high current conditions. More studies may need to be performed on a comprehensive basis. Research areas for consideration are suggested, however, these research and or qualification/standard test areas are not all inclusive and should not be construed as the element (s) that delivers any potential copper wire bond solution. A false sense of security may occur, whenever there is a reliance on passing any particular qualification, standard, or test protocol.
The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.
The purpose of this test was to determine the heavy ion-induced single-event effect (SEE) susceptibility of the Samsung solid state drive (SSD) containing the Vertical-NAND (VNAND) flash technology. This test was supported by the NASA Electronics Parts and Packaging (NEPP) Program.
An overview of the 2020 single event effects FPGA effort performed by the NASA Electronic Parts and Packaging Group is presented. Information includes Heavy-ion data for the following FPGA devices: Xilinx Kintex-UltraScale and Microsemi PolarFire. Future work is presented.
An overview of the 2020 single event effects FPGA effort performed by the NASA Electronic Parts and Packaging Group is presented. Information includes Heavy-ion data for the following FPGA devices: Xilinx Kintex-UltraScale and Microsemi PolarFire. Future work is presented.
This work is sponsored by the NASA Electronic Parts and Packaging (NEPP) Program. One of the objectives of this task is to prepare a body of knowledge guideline document summarizing the CMOS technology scaling impact on CMOS parts and parts reliability for space applications. Scaling impact on parts radiation sensitivity is not addressed in this report.
The NASA Electronic Parts and Packaging (NEPP) Program Sensor Technology Commercial Sensor Survey task is geared toward benefiting future NASA space missions with low-cost, short-duty-cycle, visible-wavelength imaging needs. Such applications could include imaging for educational outreach purposes or short surveys of spacecraft, planetary, or lunar surfaces. Under the task, inexpensive, low-power, commercial grade CMOS sensors were surveyed in fiscal year 2007 (FY07), and three sensors were selected and tested for total ionizing dose (TID) and displacement damage dose (DDD) tolerance in fiscal year 2008 (FY08). The selected sensors had to meet selection criteria chosen to support small, low-mass cameras that produce good resolution color images. The commercial CMOS sensors tested under the task in FY08 showed very promising response to typical outreach and survey camera TID and DDD levels. In fiscal year 2009 (FY09), the survey was broadened to include two additional, similar sensor products. This compendium provides results for all radiation testing performed on the Micron and OmniVision sensors that were selected for radiation tolerance testing in FY08 and FY09.
This report is the result of funding by the NASA Electronic Parts and Packaging Program (NEPP) and the combined efforts of members within the Xilinx Radiation Test Consortium (XRTC), sometimes known as the Xilinx Single Event Effects (SEE) Test Consortium. The XRTC is a voluntary association of aerospace entities, including leading aerospace companies, universitie and national laboratories, combining resources to characterize reconfigurable, field programmable gate arrays (FPGAs) for aerospace applications. Previous publications of Virtex-4 radiation results are for commercial (non-epitaxial) devices; see, for example, Refs. 1–5. A notable exception is Ref. 6, which presents XRTC upset measurements of storage elements in the PowerPC405s in the XQR4VFX60. This work represents a continuation of the efforts reported in the “Virtex-4QV Static SEU Characterization Summary” [7]. The contents of this report describe various Single Event Functional Interrupt (SEFI) and Single Event Upset (SEU) modes seen while dynamically exercising the clocked resources within Virtex-4 devices and the corresponding mitigation techniques related to the aforementioned observed SEFI modes.
The National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program has been evaluating state-of-the-art Embedded Passive Technology for the printed circuit board (PCB) industry for the past several years and has conducted its own testing on embedded passive coupons (resistors and capacitors). This document is a progress report of the work performed through fiscal year 2008 by NASA and the Navy to convert an existing PWB (printed wiring board) design to a design that incorporates embedded passive components. The work is being performed through a memorandum of understanding (MOU) between the NEPP Program (NASA) and the Naval Surface Warfare Center (NSWC) Crane Emerging Critical Interconnect Technology (ECIT) Program. NSWC Crane’s ECIT Program has funding to convert two PCB designs from the military and aerospace industry to a PCB design with embedded passives. ECIT will provide a design team that will take a well characterized design and convert it to an embedded design. They will also provide electrical modeling and layout expertise as well as build the PWB in their facility in Indiana. NEPP, through the Jet Propulsion Laboratory (JPL), will assemble any passives deemed not suitable for embedding and the active components and electrically test the new design to the existing (non-embedded) design
This report documents the activities and results of the fiscal year 2009 (FY09) funding for the NASA Electronic Parts and Packaging (NEPP) program for non-volatile memory (NVM) devices. The FY09 task was divided into two main efforts: 1. Development of in-house measurement capability for flash devices 2. Reliability characterization of multi-level vs. single-level flash devices The FY09 NEPP Non Volatile Memory study was organized into these two sections in recognition of the continued and increasing importance of NVM to NASA. All NASA missions use NVM for boot code storage and some limited data archiving. Space-grade NVM has lagged commercial NVM development by many orders of magnitude, however. This gap in density only continues to increase as space-grade memories remain constant in the 1–16 Mbit levels, while commercial flash-based devices shrink in size and double in capacity every 18 months. Commercial flash devices are now at the 32 Gbit level, 10,000 times denser than current NASA NVM. This FY marks the beginning of a significant technological transition in NVM for NASA. The aggressive scaling of commercial NVMs has, as a by-product, made some of the flash devices radiation-tolerant enough to be at least considered for low-level radiation environment missions [Irom 2008]. This NEPP task is focused on understanding the reliability and potential future applications of such highly scaled flash memories.
Information used in the evaluation of design of Sunkeeper Control's electronic controllers and hydronic packages is discussed. This information includes system performance specifications, a design data brochure, drawings, and qualification and acceptance test procedures.
This invention is an electronically commutated brushless motor controller that incorporates Hall-array sensing in a small, 42-gram package that provides 4096 absolute counts per motor revolution position sensing. The unit is the size of a miniature hockey puck, and is a 44-pin male connector that provides many I/O channels, including CANbus, RS-232 communications, general-purpose analog and digital I/O (GPIO), analog and digital Hall inputs, DC power input (18-90 VDC, 0-l0 A), three-phase motor outputs, and a strain gauge amplifier. This controller replaces air cooling with conduction cooling via a high-thermal-conductivity epoxy casting. A secondary advantage of the relatively good heat conductivity that comes with ultra-small size is that temperature differences within the controller become smaller, so that it is easier to measure the hottest temperature in the controller with fewer temperature sensors, or even one temperature sensor. Another size-sensitive design feature is in the approach to electrical noise immunity. At a very small size, where conduction paths are much shorter than in conventional designs, the ground becomes essentially isopotential, and so certain (space-consuming) electrical noise control components become unnecessary, which helps make small size possible. One winding-current sensor, applied to all of the windings in fast sequence, is smaller and wastes less power than the two or more sensors conventionally used to sense and control winding currents. An unexpected benefit of using only one current sensor is that it actually improves the precision of current control by using the "same" sensors to read each of the three phases. Folding the encoder directly into the controller electronics eliminates a great deal of redundant electronics, packaging, connectors, and hook-up wiring. The reduction of wires and connectors subtracts substantial bulk and eliminates their role in behaving as EMI (electro-magnetic interference) antennas. A shared knowledge by each motor controller of the state of all the motors in the system at 500 Hz also allows parallel processing of higher-level kinematic matrix calculations.
Test probe, in conjunction with standard equipment, tests axial-lead electronic components in their original packages. The probe can be modified to test any electronic component with automatic or nonautomatic equipment.
Advanced hermetic packages developed to house electronic circuits operating at frequencies from 1 to 100 gigahertz and beyond. Signals coupled into and out of packages electromagnetically. Provides circuit packages small, lightweight, rugged, and inexpensive in mass production. Packages embedded in planar microstrip and coplanar waveguide circuits, in waveguide-to-planar and planar-to-waveguide circuitry, in waveguide-to-waveguide circuitry, between radiating (antenna) elements, and between planar transmission lines and radiating elements. Other applications in automotive, communication, radar, remote sensing, and biomedical electronic systems foreseen.
JPL along with other aerospace agencies such as the US Air Force Space Pro-grams and a packaging technology innovator, i3 Electronics, Inc., are evaluating the use of state-of-the-art (SOA) commercial off-the-shelf (COTS) and alternative packaging technologies for future high performance and high reliability space applications. Utilization of SOA COTS technologies have resulted in large scale reduction in electronics volume, weight, power, cost and schedule with outstanding electrical performance and high reliability. We will share JPL’s joint design, architectural approach, alternative substrate materials selection, associated processes, and mission assurance role in identifying reliability and qualification risks, as part of the three year Heterogeneous Packaging/Device Integration effort under the guidance and leadership of JPL’s Mission Assurance Directorate.
The Hydrogen Maser Clock (HMC) project was originally conceived to fly on a reflight of the European Space Agency (ESA) free flying platform, the European Recoverable Carrier (EURECA) that had been launched into space and recovered by NASA's Space Transportation System (STS). A Phase B study for operation of HMC as one of the twelve EURECA payload components was begun in July 1991, and completed a year later. Phase C/D of HMC began in August 1992 and continued into early 1995. At that time ESA decided not to refly EURECA, leaving HMC without access to space. Approximately 80% of the flight support electronics are presently operating the HMC's physics package in a vacuum tank at the Smithsonian Astrophysical Observatory, and are now considered to be well-tested flight electronics. The package will continue to be operated until the end of 1997 or until a flight opportunity becomes avaiable. Appendices: letters and trip report; proceedings of the symposium on frequency standards and metrology; milli-celsius-stability thermal control for an orbiting frequency standard.
This slide presentation reviews packaging challenges and options for electronic parts. The presentation includes information about non-hermetic packages, space challenges for packaging and complex package variations.