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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 469 records · Page 26
All sourcesNASA NTRSDOE OSTI
NASA NTRS2016

Evaluation of 10V Chip Polymer Tantalum Capacitors for Space Applications

Due to low ESR and safe failure mode, new technology chip polymer tantalum capacitors (CPTC) have gained popularity in the electronics design community, first in commercial applications, and now in hi-rel and space systems. The major drawbacks of these parts are high leakage currents, degradation under environmental stresses, and a relatively narrow temperature range of operating and storage conditions. Several studies have shown that a certain amount of moisture in polymer cathodes is necessary for a normal operation of the parts. This might limit applications of CPTCs in space systems and requires analysis of long-term exposure to deep vacuum conditions on their performance and reliability. High leakage currents and limited maximum operational temperature complicate accelerated testing that is necessary to assess long-term reliability and require new screening and qualification procedures for quality assurance. A better understanding of behavior of CPTCs as compared to traditional, MnO2, capacitors is necessary to develop adequate approaches for QA system for space applications. A specific of CPTCs is that different materials and processes might be used for low-voltage (10 V and less) and high-voltage (above 10 V) capacitors, so performance and degradation processes in these groups require separate analysis. In this work, that is a part of the NASA Electronic Parts and Packaging (NEPP) program, degradation of AC and DC characteristics under environmental stresses at different temperatures and voltages have been studied in nine lots of commercial and automotive grade capacitors rated to 10 V. Results of analysis of leakage currents, high temperature storage (HTS) up to 5000 hrs in vacuum and air at different temperatures, and Highly Accelerated Life Testing (HALT) in the range from 85 C to 145 C are presented. Temperature and voltage acceleration factors were calculated based on approximation of distributions of degradation rates with a general log-linear Weibull model. Mechanisms of degradation and failures, and requirements for screening and qualification testing are discussed.

Tantalum Capacitors↗
NASA NTRS2017

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

Field Programmable Gate Array (FPGA); Triple Modul↗
NASA NTRS2017

DDR Memories

This presentation will include information about Double Data Rate (DDR) technology, NASA Electronic Parts and Packaging (NEPP) tasks and their purpose, collaborations, a roadmap, NEPP partners, results to date, and future plans.

Double Data Rate (DDR)↗
NASA NTRS2017

Graphics Processor Units (GPUs)

This presentation will include information about Graphics Processor Units (GPUs) technology, NASA Electronic Parts and Packaging (NEPP) tasks, The test setup, test parameter considerations, lessons learned, collaborations, a roadmap, NEPP partners, results to date, and future plans.

Single Event Effect (SEE) testing↗
NASA NTRS2017

Silicon Power MOSFETs

Recent work for the NASA Electronic Parts and Packaging Program Power MOSFET task is presented. The Task technology focus, roadmap, and partners are given. Recent single-event effect test results on commercial, automotive, and radiation hardened trench power MOSFETs are summarized with an emphasis on risk of using commercial and automotive trench-gate power MOSFETs in space applications.

trench-gate MOSFET↗
NASA NTRS2017

Proton Irradiation of the 16GB Intel Optane SSD

The purpose of this test is to assess the single event effects (SEE) and radiation susceptibility of the Intel Optane Memory device (SSD) containing the 3D Xpoint phase change memory (PCM) technology. This test is supported by the NASA Electronics Parts and Packaging Program (NEPP).

Single-Event Effects (SEE)↗
NASA NTRS2009

Optical Fiber Assemblies for Space Flight from the NASA Goddard Space Flight Center, Photonics Group

The Photonics Group at NASA Goddard Space Flight Center in the Electrical Engineering Division of the Advanced Engineering and Technologies Directorate has been involved in the design, development, characterization, qualification, manufacturing, integration and anomaly analysis of optical fiber subsystems for over a decade. The group supports a variety of instrumentation across NASA and outside entities that build flight systems. Among the projects currently supported are: The Lunar Reconnaissance Orbiter, the Mars Science Laboratory, the James Webb Space Telescope, the Express Logistics Carrier for the International Space Station and the NASA Electronic Parts. and Packaging Program. A collection of the most pertinent information gathered during project support over the past year in regards to space flight performance of optical fiber components is presented here. The objective is to provide guidance for future space flight designs of instrumentation and communication systems.

Ott, Melanie N.↗
NASA NTRS2018

ASIC/FPGA Trust Assessment Framework

NASA Electronic Parts and Packaging (NEPP) is developing a process to be employed in critical applications. The framework assesses levels of Trust and assurance in microelectronic systems. The process is being created with participation from a variety of organizations. We present a synopsis of the framework that includes contributions from The Aerospace Corporation.

Application specific integrated circuit (ASIC)↗
NASA NTRS2018

Government Microelectronics Assessment for Trust (GOMAT)

NASA Electronic Parts and Packaging (NEPP) is developing a process to be employed in critical applications. The framework assesses levels of trust and assurance in microelectronic systems. The process is being created with participation from a variety of organizations. We present a synopsis of the framework that includes contributions from The Aerospace Corporation.

Assurance↗
NASA NTRS2018

Update - Body of Knowledge (BOK) for Copper Wire Bonds

Copper wire bond technology developments continue to be a subject of technical interest to the NASA (National Aeronautics and Space Administration) NEPP (NASA Electronic Parts and Packaging Program) which funded this update. Based on this new research, additional copper bond wire vulnerabilities were found in the literature - Crevice corrosion, intrinsic degradation of palladium coated copper wire, congregation of palladium near ball bond interface leading to failure, residual aluminum pad metallization impact on device lifetimes, stitch cracking phenomena, package delamination's that have resulted in wire bond failures and device failure due to elemental sulfur. A search of the U.S.A. patent web site found 3 noteworthy patents on the following developments: claim of a certain IMC (Intermetallic Compound) thickness as a mitigation solution to chlorine corrosion; claim of using materials with different pHs to neutralize contaminants in a package containing copper wire bonds; and a discussion on ball shear test threshold values for different applications. In addition, an aerospace contractor of military hardware had a presentation on copper bond wires where it was reported that there was a parametric shift and noise susceptibility of devices with copper bond wires which affected legacy design performance. A review of silver bond wire (another emerging technology) technical papers found that an electromigration failure mechanism was evident in device applications that operate under high current conditions. More studies may need to be performed on a comprehensive basis. Research areas for consideration are suggested, however, these research and or qualification/standard test areas are not all inclusive and should not be construed as the element (s) that delivers any potential copper wire bond solution. A false sense of security may occur, whenever there is a reliance on passing any particular qualification, standard, or test protocol.

Rutkowski, E.↗
NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗