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At least 487 records · Page 27

BULKI-Store v0.3.2

BULKI-Store is a distributed object storage system optimized for high-performance computing environments. Built with a Rust core and Python bindings, it efficiently manages scientific and machine learning datasets across HPC clusters. The system employs a client-server architecture with MPI integration, enabling seamless scaling on supercomputers like Perlmutter. BULKI-Store's object-oriented approach provides intuitive data organization with rich metadata support, contrasting with traditional file-based solutions. Key optimizations include selective checkpoint loading, unified checkpoint files, and object chunking for large data transfers. For machine learning workloads, BULKI-Store offers advantages through fine-grained access patterns, dynamic data sharing between training instances, and reduced memory pressure. Memory management features include strategic Python GC calls, minimized data copies, and batch processing capabilities. The system leverages Rayon's thread pool for asynchronous data prefetching and supports multiple CPU architectures (ARM64, x86, AMD, RISC-V). By combining performance optimizations with developer-friendly APIs, BULKI-Store addresses the complex data management challenges of modern HPC applications while maintaining compatibility across heterogeneous computing environments.

Zhang, Wei [Lawrence Berkeley National Laboratory ↗

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

A scalable superconducting nanowire memory array with row–column addressing

Scalable superconducting memory is required for the development of low-energy superconducting computers and fault-tolerant quantum computers. Conventional superconducting logic-based memory cells possess a large footprint that limits scaling; nanowire-based superconducting memory cells, although more compact, have high error rates, which hinders integration into large arrays. Here we report a 4 × 4 superconducting nanowire memory array that is designed for scalable row–column operations and has a functional density of 2.6 Mbit cm −2 . Each memory cell is based on a nanowire loop consisting of two temperature-dependent superconducting switches and a variable kinetic inductor. The arrays operate at 1.3 K, where we implement and characterize multiflux quanta state storage and destructive read-out. By optimizing the write- and read-pulse sequences, we minimize bit errors and maximize operating margins. We achieve a minimum bit error rate of 10 −5 . Here, we also use circuit-level simulations to understand the memory cell’s dynamics, performance limits and stability under varying pulse amplitudes.

Electrical and electronic engineering↗

SU-E-T-258: Parallel Optimization of Beam Configurations for CyberKnife Treatments

Purpose: The CyberKnife delivers a large number of beams originating at different non-planar positions and with different orientation. We study how much the quality of treatment plans depends on the beams considered during plan optimization. Particularly, we evaluate a new approach to search for optimal treatment plans in parallel by running optimization steps concurrently. Methods: So far, no deterministic, complete and efficient method to select the optimal beam configuration for robotic SRS/SBRT is known. Considering a large candidate beam set increases the likelihood to achieve a good plan, but the optimization problem becomes large and impractical to solve. We have implemented an approach that parallelizes the search by solving multiple linear programming problems concurrently while iteratively resampling zero weighted beams. Each optimization problem contains the same set of constraints but different variables representing candidate beams. The search is synchronized by sharing the resulting basis variables among the parallel optimizations. We demonstrate the utility of the approach based on an actual spinal case with the objective to improve the coverage. Results: The objective function is falling and reaches a value of 5000 after 49, 31, 25 and 15 iterations for 1, 2, 4, and 8 parallel processes. This corresponds to approximately 97% coverage in 77%, 59%, and 36% of the mean number of iterations with one process for 2, 4, and 8 parallel processes, respectively. Overall, coverage increases from approximately 91.5% to approximately 98.5%. Conclusion: While on our current computer with uniform memory access the reduced number of iterations does not translate into a similar speedup, the approach illustrates how to effectively parallelize the search for the optimal beam configuration. The experimental results also indicate that for complex geometries the beam selection is critical for further plan optimization.

07 ISOTOPE AND RADIATION SOURCES↗

About the deformation of ferroelectric hystereses

Studying ferroelectric hafnium oxide with focus on memory applications for the past years, discussions frequently involved the shape of measured polarization hystereses, its relation to the device performance, and how to optimize it. A perfect model-like hysteresis is of nearly rectangular shape and all deviations from this situation have to have a certain physical origin. Different phenomena and their impact on the shape of the polarization hystereses were reported in literature: Aging, imprint, fatigue, or dielectric interface layers to name a few examples. A collection of these phenomena is not easily found up to now. Thus, filling or at least reducing this gap is one of the goals of this work. Moreover, observing a pinched, slanted, or displaced hysteresis, it is quite tempting to try the reverse approach: a derivation of potential structural origins for this curve shape. First, the basics of the dynamic hysteresis measurement and the ferroelectric memories are briefly reviewed. The figures of interest are derived to ensure a proper assessment of imperfections in the hysteresis shape and their influence. It is discussed how a closer look on the polarization loop helps to draw conclusions on what might have caused such a shape or at least how to rule out some phenomena if the expected indications are not reflected in the present curve. Of course, further structural or electrical studies, as they are exemplarily pointed out, are indispensable to find the root cause(s) for the deviations from the ideal hysteresis. But sophisticated methods are not always accessible straightaway and, moreover, a pointer on where to start is always helpful. Especially, the transient currents recorded during a dynamic hysteresis measurement are stressed as a valuable instrument for this purpose. Despite their known potential, these currents are seldom shown in literature.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Correlation Between Corrugation-Induced Flexoelectric Polarization and Conductivity of Low-Dimensional Transition Metal Dichalcogenides

The tunability of polar and semiconducting properties of low-dimensional transition metal dichalcogenides (TMDs) have propelled them to the forefront of fundamental and applied physical research. These materials can vary their electrophysical properties from nonpolar to ferroelectric, and from direct-band semiconducting to metallic. In addition to classical controlling factors, such as field effect, composition, and doping, new degrees of freedom emerge in TMDs due to the curvature-induced electron redistribution and the associated changes in electronic properties. Here we theoretically explore the elastic and electric fields, flexoelectric polarization and free charge density for a TMD nanoflake placed on a rough substrate with a sinusoidal corrugation profile. Finite element modelling results for different flake thickness and corrugation depth yield insights into the flexoelectric nature of the out-of-plane electric polarization and establish the unambiguous correlation between the polarization and static conductivity modulation. The modulation is caused by the coupling between the deformation potential and inhomogeneous elastic strains, which evolve in the TMD nanoflake due to the adhesion between the flake surface and corrugated substrate. We reveal a pronounced maximum in the thickness dependences of the electron and hole conductivity of MoS 2 and MoTe 2 nanoflakes placed on a corrugated substrate, which opens the way for the optimization of their geometry towards significant improvement in their polar and electronic properties, necessary for advanced applications in nanoelectronics and memory devices. Specifically, the obtained results can be useful for the development of nanoscale straintronic devices based on the bended MoS 2 , MoTe 2 , and MoSTe nanoflakes, such as diodes and bipolar transistors with a bending-controllable sharpness of p-n junctions.

42 ENGINEERING↗

Improving I/O-aware Workflow Scheduling via Data Flow Characterization and trade-off Analysis

The scientific computing paradigm has transitioned from compute-intensive to I/O-intensive and memory-intensive in the past decade, especially when data-driven science has become common practice. Numerous empirical I/O-aware scheduling optimizations have been developed by incorporating I/O capacity and bandwidth as constraints into scheduling. Unfortunately, there is a lack of data flow (I/O) characterization tool and an understanding of trade-offs between concurrency, locality, and I/O bandwidth. To bridge the gap, this work 1) presents a set of descriptors to characterize, organize, and visualize I/O profiles, including flow size, I/O bandwidth, and operation count, which group data flows by I/O types, tasks, and files; 2) proposes an I/O Roofline model-based trade-off analysis to find the optimal trade-off between flow operational intensity, concurrency, and flow performance. The I/O descriptors generate useful insights into complicated I/O behaviors, suggesting distinct concurrency, storage, and scheduling to be used by types, tasks, and files. The proposed trade-off analysis guides scheduling decisions that generate resource assignment with the best flow parallelism. We evaluate our I/O-aware scheduling methodology on a highly I/O-intensive workflow–1000 Genomes. The experimental results demonstrate speedups of up to 2.4× compared to the state-of-the- art methods.

Guo, Luanzheng [BATTELLE (PACIFIC NW LAB)]↗

Trace: a high-throughput tomographic reconstruction engine for large-scale datasets

Abstract Background Modern synchrotron light sources and detectors produce data at such scale and complexity that large-scale computation is required to unleash their full power. One of the widely used imaging techniques that generates data at tens of gigabytes per second is computed tomography (CT). Although CT experiments result in rapid data generation, the analysis and reconstruction of the collected data may require hours or even days of computation time with a medium-sized workstation, which hinders the scientific progress that relies on the results of analysis. Methods We present Trace, a data-intensive computing engine that we have developed to enable high-performance implementation of iterative tomographic reconstruction algorithms for parallel computers. Trace provides fine-grained reconstruction of tomography datasets using both (thread-level) shared memory and (process-level) distributed memory parallelization. Trace utilizes a special data structure called replicated reconstruction object to maximize application performance. We also present the optimizations that we apply to the replicated reconstruction objects and evaluate them using tomography datasets collected at the Advanced Photon Source. Results Our experimental evaluations show that our optimizations and parallelization techniques can provide 158× speedup using 32 compute nodes (384 cores) over a single-core configuration and decrease the end-to-end processing time of a large sinogram (with 4501 × 1 × 22,400 dimensions) from 12.5 h to <5 min per iteration. Conclusion The proposed tomographic reconstruction engine can efficiently process large-scale tomographic data using many compute nodes and minimize reconstruction times.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Proactive Data Containers for Scientific Storage (Final Report)

Emerging HPC systems are expected to be deployed with an unprecedented level of complexity, due to a deep system memory/storage hierarchy and heterogeneity of the storage hardware. This hierarchy is expected to range from CPU cache through several levels of volatile memory to nonvolatile memory, traditional hard disks, and tape. Simple and efficient methods of data management and movement through this hierarchy is critical for scientific applications using exascale systems. Existing storage system and I/O (SSIO) technologies face severe challenges in dealing with these requirements. POSIX and MPI I/O standards that are the basis for existing I/O libraries and parallel file systems present fundamental challenges in the areas of scalable metadata operations, semantics-based data movement performance tuning, asynchronous operation, and support for scalable consistency of distributed operations. Moving toward new paradigms for SSIO in the extreme-scale era, we have proposed to investigate novel object-based data abstractions and storage mechanisms that take advantage of the deep storage hierarchy and enable proactive automated performance tuning. In order to achieve these overarching goals, we initiated an effort to develop a fundamental new data abstraction, called Proactive Data Containers (PDC). A PDC is a container within a locus of storage (memory, NVRAM, disk, etc.) that stores science data in an object-centric manner. Managing data as objects enables powerful optimization opportunities for data movement and transformations. The R&D focus of this project are: 1) formulation of object-oriented PDCs and their mapping in different levels of the exascale storage hierarchy; 2) efficient strategies for moving data in deep storage hierarchies using PDCs; 3) techniques for transforming and reorganizing data based on application requirements; and 4) novel analysis paradigms for enabling data transformations and user-defined analysis on data in PDCs. Toward achieving these overarching goals, we designed an object-centric application programing interface (API) for HPC, scalable metadata management for object-centric storage systems, and data movement optimizations such as Data Elevator for moving data between two levels of storage devices and TAPIOCA for efficient aggregation of data on compute nodes. We then implemented several components of the PDC system. They include metadata management, data placement services, remote procedure calls, data aggregation, etc. We have put them together into the overall PDC framework.

97 MATHEMATICS AND COMPUTING↗

A Brief Summary on Formalizing Parallel Tensor Distributions, Redistributions, and Algorithm Derivations

Large-scale datasets in computational chemistry typically require distributed-memory parallel methods to perform a special operation known as tensor contraction. Tensors are multidimensional arrays, and a tensor contraction is akin to matrix multiplication with special types of permutations. Creating an efficient algorithm and optimized implementation in this domain is complex, tedious, and error-prone. To address this, we develop a notation to express data distributions so that we can apply use automated methods to find optimized implementations for tensor contractions. We consider the spin-adapted coupled cluster singles and doubles method from computational chemistry and use our methodology to produce an efficient implementation. Experiments per- formed on the IBM Blue Gene/Q and Cray XC30 demonstrate impact both improved performance and reduced memory consumption.

97 MATHEMATICS AND COMPUTING↗

Domain wall-magnetic tunnel junction spin–orbit torque devices and circuits for in-memory computing

There are pressing problems with traditional computing, especially for accomplishing data-intensive and real-time tasks, that motivate the development of in-memory computing devices to both store information and perform computation. Magnetic tunnel junction memory elements can be used for computation by manipulating a domain wall, a transition region between magnetic domains, but the experimental study of such devices has been limited by high current densities and low tunnel magnetoresistance. Here, we study prototypes of three-terminal domain wall-magnetic tunnel junction in-memory computing devices that can address data processing bottlenecks and resolve these challenges by using perpendicular magnetic anisotropy, spin–orbit torque switching, and an optimized lithography process to produce average device tunnel magnetoresistance TMR = 171% and average resistance-area product RA = 29 Ω μm2, close to the RA of the unpatterned film. Device initialization variation in switching voltage is shown to be curtailed to 7%–10% by controlling the domain wall initial position, which we show corresponds to 90%–96% accuracy in a domain wall-magnetic tunnel junction full adder simulation. Repeatability of writing and resetting the device is shown. A circuit shows an inverter operation between two devices, showing that a voltage window is large enough, compared to the variation noise, to repeatably operate a domain wall-magnetic tunnel junction circuit. These results make strides in using magnetic tunnel junctions and domain walls for in-memory and neuromorphic computing applications.

Alamdar, Mahshid (ORCID:0000000221732935)↗

DISP: Optimizations towards Scalable MPI Startup

Despite the popularity of MPI for high performance computing, the startup of MPI programs faces a scalability challenge as both the execution time and memory consumption increase drastically at scale. We have examined this problem using the collective modules of Cheetah and Tuned in Open MPI as representative implementations. Previous improvements for collectives have focused on algorithmic advances and hardware off-load. In this paper, we examine the startup cost of the collective module within a communicator and explore various techniques to improve its efficiency and scalability. Accordingly, we have developed a new scalable startup scheme with three internal techniques, namely Delayed Initialization, Module Sharing and Prediction-based Topology Setup (DISP). Our DISP scheme greatly benefits the collective initialization of the Cheetah module. At the same time, it helps boost the performance of non-collective initialization in the Tuned module. We evaluate the performance of our implementation on Titan supercomputer at ORNL with up to 4096 processes. The results show that our delayed initialization can speed up the startup of Tuned and Cheetah by an average of 32.0% and 29.2%, respectively, our module sharing can reduce the memory consumption of Tuned and Cheetah by up to 24.1% and 83.5%, respectively, and our prediction-based topology setup can speed up the startup of Cheetah by up to 80%.

Fu, Huansong↗

Tula: Optimizing Time, Cost, and Generalization in Distributed Large-Batch Training

Distributed training increases the number of batches processed per iteration either by scaling-out (adding more nodes) or scaling-up (increasing the batch-size). However, the largest configuration does not necessarily yield the best performance. Horizontal scaling introduces additional communication overhead, while vertical scaling is constrained by computation cost and device memory limits. Thus, simply increasing the batch-size leads to diminishing returns: training time and cost decrease initially but eventually plateaus, creating a knee-point in the time/cost vs. batch-size pareto curve. The optimal batch-size therefore depends on the underlying model, data and available compute resources. Large batches also suffer from worse model quality due to the well-known “generalization gap”. In this paper, we present Tula, an online service that automatically optimizes time, cost, and convergence quality for large-batch training of convolutional models. It combines parallel-systems modeling with statistical performance prediction to identify the optimal batchsize. Tula predicts training time and cost within 7.5−14% error across multiple models, and achieves up to 20× overall speedup and improves test accuracy by ≈9% on average over standard large-batch training on various vision tasks, thus successfully mitigating the generalization gap and accelerating training at the same time.

Tyagi, Sahil [ORNL] (ORCID:0009000783144745)↗

Exploring Machine Learning Techniques For Dynamic Modeling on Future Exascale Systems

Future exascale systems must be optimized for both power and performance at scale in order to achieve DOE’s goal of a sustained petaflop within 20 Megawatts by 2022 [1]. Massive parallelism of the future systems combined with complex memory hierarchies will form a barrier to efficient application and architecture design. These challenges are exacerbated with emerging complex architectures such as GPGPUs and Intel Xeon Phi as parallelism increases orders of magnitude and system power consumption can easily triple or quadruple. Therefore, we need techniques that can reduce the search space for optimization, isolate power-performance bottlenecks, identify root causes for software/hardware inefficiency, and effectively direct runtime scheduling.

Song, Shuaiwen↗

An adaptive Hessian approximated stochastic gradient MCMC method

Bayesian approaches have been successfully integrated into training deep neural networks. One popular family is stochastic gradient Markov chain Monte Carlo methods (SG-MCMC), which have gained increasing interest due to their ability to handle large datasets and the potential to avoid overfitting. Although standard SG-MCMC methods have shown great performance in a variety of problems, they may be inefficient when the random variables in the target posterior densities have scale differences or are highly correlated. Here, we present an adaptive Hessian approximated stochastic gradient MCMC method to incorporate local geometric information while sampling from the posterior. The idea is to apply stochastic approximation (SA) to sequentially update a preconditioning matrix at each iteration. The preconditioner possesses second-order information and can guide the random walk of a sampler efficiently. Instead of computing and saving the full Hessian of the log posterior, we use limited memory of the samples and their stochastic gradients to approximate the inverse Hessian-vector multiplication in the updating formula. Moreover, by smoothly optimizing the preconditioning matrix via SA, our proposed algorithm can asymptotically converge to the target distribution with a controllable bias under mild conditions. To reduce the training and testing computational burden, we adopt a magnitude-based weight pruning method to enforce the sparsity of the network. Our method is user-friendly and demonstrates better learning results compared to standard SG-MCMC updating rules. The approximation of inverse Hessian alleviates storage and computational complexities for large dimensional models. Numerical experiments are performed on several problems, including sampling from 2D correlated distribution, synthetic regression problems, and learning the numerical solutions of heterogeneous elliptic PDE. The numerical results demonstrate great improvement in both the convergence rate and accuracy.

97 MATHEMATICS AND COMPUTING↗

Intelligent Experiments through Real-Time AI: Fast Data Processing and Autonomous Detector Control for High-Energy Nuclear Experiments

The aim of this project is to develop software and hardware for fast real-time data processing and autonomous detector control and calibration for the sPHENIX and the future EIC experiments. Below summarizes Georgia Tech team efforts in the past year: 1. We developed a real-time clustering algorithm and FPGA-based pipeline architecture for processing fired pixel data from ALPIDE sensors in sPHENIX experiments. Our Columnar Clustering Co-Design introduces a hardware-aware, stream-friendly approach that segments pixel data by column pairs using a Column Pair Clustering (CPC) strategy, followed by Cluster Stitching to merge adjacent subclusters. Implemented in Vitis HLS, the pipeline comprises five stages—read-in, subclustering, stitching, analysis, and write-out—connected by tagged HLS streams with custom end-of-event signaling for robust synchronization. We designed a pipelined dataflow model optimized for throughput, low latency, and minimal buffering, enabling scalable clustering across events of arbitrary size. Our system maintains spatial precision via center-of-mass and shape key extraction and efficiently handles edge cases such as fragmented or nested clusters. Compared against DBSCAN in both software and hardware, our approach demonstrates competitive performance under FPGA constraints. 2. We also conducted a comprehensive algorithm-to-hardware co-design of connected component analysis tailored for sPHENIX experiments, focusing on real-time, low-latency processing using FPGAs and High-Level Synthesis (HLS). Starting from a Python-based particle tracking pipeline, the team translated the core logic—graph traversal via DFS and Union-Find—into an HLS-compatible C++ model, replacing dynamic memory and recursion with static arrays and pipelined control flow. The final design includes a fully streamed and dataflow-compatible Union-Find kernel optimized across five iterations, incorporating loop pipelining, array partitioning, AXI/FIFO interface tuning, and function flattening. Experimental results show up to 14.8× speedup over the CPU baseline, reducing per-graph latency to 1.58 μs and demonstrating strong resource efficiency with only ~7k LUTs and zero BRAM usage. The design maintains functional correctness against the Python reference using a Python-based C-simulation framework and Mean Squared Error metrics. This work validates the potential of HLS-driven FPGA designs for edge-level HEP data acquisition, laying a scalable foundation for future integration with real-time detector pipelines and multi-graph processing systems.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

GrainNN: A neighbor-aware long short-term memory network for predicting microstructure evolution during polycrystalline grain formation

High fidelity simulations of grain formation in alloys are an indispensable tool for process-to-mechanical-properties characterization. Such simulations, however, can be computationally expensive as they require fine spatial and temporal discretizations. Their cost becomes an obstacle to parametric studies and ensemble runs and ultimately makes downstream tasks like optimal control and uncertainty quantification challenging. To enable such downstream tasks, we introduce GrainNN, an efficient and accurate reduced-order model for epitaxial grain growth in additive manufacturing conditions. GrainNN is a sequence-to-sequence long-short-term-memory (LSTM) deep neural network that evolves the dynamics of manually crafted features. Its innovations are (1) an attention mechanism with grain-microstructure-specific transformer architecture; and (2) an overlapping combination of several clones of the network to generalize to grain configurations that are different from those used for training. This design enables GrainNN to predict grain formation for unseen physical parameters, grain number, domain size and geometry. Furthermore, GrainNN not only reconstructs the quantities of interest but also can be pointwise accurate. In our numerical experiments, we use a polycrystalline phase field method to both generate the training data and assess GrainNN. For multiparametric, ensemble simulations with many grains, GrainNN can be orders of magnitude faster than phase field simulations, while delivering 5%–15% pointwise error. Additionally, this speedup includes the cost of the phase field simulations for generating training data.

36 MATERIALS SCIENCE↗

AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators

Tensor algebra operations represent an important class of algorithms used across many applications, including machine learning, scientific computing, and data analytics. As a result, the efficient generation of custom accelerators for tensor operations has received increased attention. Previous efforts have produced automated tools enabling users to prototype and explore optimized accelerators. However, little effort has been focused on the host-accelerator interaction in these tools. Efficient use of hardware accelerators requires knowledge about the accelerator's capabilities (operations, data formats, and opcode support), the host CPU microarchitecture (e.g., memory hierarchy), the host-accelerator interface, and the application's features (which code regions should be mapped onto an accelerator). Manually rewriting the original applications to facilitate improved custom accelerator mapping is an error-prone and time-consuming endeavor. To cope with this, we propose AXI4MLIR, a new framework to automatically generate and optimize the communication between the host CPU and arbitrary accelerators that implement linear algebra algorithms. AXI4MLIR extends the MLIR compiler framework to automatically generate efficient host-accelerator driver code for accelerators with AXI-based interfaces. Our compiler extensions enable automatic driver code generation while carefully considering the host's memory hierarchy and target accelerator features. To demonstrate the flexibility and utility of AXI4MLIR, we test it with diverse use cases that include different types of accelerators, tiling scenarios, and dataflow schemes. We compare our experimental results to manual implementations of host-accelerator driver code and find that our approach can reduce CPU cache references by 56% and deliver up to a 1.65x speedup.

Bohm Agostini, Nicolas↗