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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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High electron mobility recovery in AlGaN/GaN 2DEG channels regrown on etched surfaces
Not Available
Energy-dependent etching-related impacts on CR-39 alpha detection efficiency for the Rn-222 and Rn-220 decay chains
Not provided.
Simulation of nonlinear superconducting rf losses derived from characteristic topography of etched and electropolished niobium surfaces
Not Available
Nanoscale x-ray imaging of circuit features without wafer etching
Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20–40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300-μm-thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240-μm thickness was used to eliminate image contrast caused by Si wafer surface scratches. Here, by using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.
Simulation and Design of Step-Etched Junction Termination Extensions for GaN Power Diodes.
Abstract not provided.
Passivation Mechanisms in Locally Etched P-Type Poly-Si on Silicon Nitride/Silicon Oxide Stack
Tunneling oxide passivated contacts are quickly becoming the industry standard for high-efficiency c-Si based photovoltaic cells. Further development of these structures is essential to enable higher efficiencies and better reliability of cells. By utilizing poly-Si/SixNy/SiOx stacks, very high efficiencies have been demonstrated on small area cells. In this work we investigate the cause of the excellent passivation seen by these structures and show that the primary reason of the excellent passivation seen is the blocking B diffusion to the SiOx/c -Si interface. We also show that the interface between the silicon nitride and polysilicon affects B diffusion through to the c-Si interface. Finally, we demonstrate that the composition of the nitride used is of great importance, and that an incorrect nitride composition leads to B diffusion, and is directly correlated to poor passivation performance.
Demonstration of >6.0-kV Breakdown Voltage in Large Area Vertical GaN p-n Diodes With Step-Etched Junction Termination Extensions
Vertical gallium nitride (GaN) p-n diodes have garnered significant interest for use in power electronics where high-voltage blocking and high-power efficiency are of concern. In this article, we detail the growth and fabrication methods used to develop a large area (1 mm 2 ) vertical GaN p-n diode capable of a 6.0-kV breakdown. We also demonstrate a large area diode with a forward pulsed current of 3.5 A, an 8.3-mΩ$\cdot$cm 2 differential specific ON-resistance, and a 5.3-kV reverse breakdown. In addition, we report on a smaller area diode (0.063 mm 2 ) that is capable of 6.4-kV breakdown with a differential specific ON-resistance of 10.2 mΩ$\cdot$cm 2 , when accounting for current spreading through the drift region at a 45° angle. Finally, the demonstration of avalanche breakdown is shown for a 0.063-mm 2 diode with a room temperature breakdown of 5.6 kV. In this work, these results were achieved via epitaxial growth of a 50-μm drift region with a very low carrier concentration of <1×10 15 cm –3 and a carefully designed four-zone junction termination extension.
Etched and Regrown Vertical GaN Junction Barrier Schottky Diodes.
Abstract not provided.