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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 523 records · Page 29

INTEGRAL core programme

The International Gamma Ray Astrophysics Laboratory (INTEGRAL) mission is described with emphasis on the INTEGRAL core program. The progress made in the planning activities for the core program is reported on. The INTEGRAL mission has a nominal lifetime of two years with a five year extension option. The observing time will be divided between the core program (between 30 and 35 percent during the first two years) and general observations. The core program consists of three main elements: the deep survey of the Galactic plane in the central radian of the Galaxy; frequent scans of the Galactic plane in the search for transient sources, and pointed observations of several selected sources. The allocation of the observation time is detailed and the sensitivities of the observations are outlined.

Gehrels, N.↗

Current Radiation Issues for Programmable Elements and Devices

The purpose of this presentation is to discuss the COTS performance, clock upset / single event transient, device configuration upset, antifuse hardening, heavy ion SEU, total dose, proton sensitivities, latchup, and additional information and data.

Katz, Richard↗

The NASA Exobiology Programme

NASA will indeed conduct a more active search for life beyond Earth. Research on the Martian meteorites will be augmented by $2 million to be contributed equally by NASA and NSF (National Science Foundation). The science strategy for the NASA Mars Surveyor Program now places a much higher priority on the search for life, particularly fossil evidence. This program features two launches per opportunity (every two years, starting this November). The focus on Exobiology emphasizes high resolution multispectral orbital mapping to locate key aqueous sedimentary minerals, the exploration of ancient terrains by capable rovers, and the need for multiple sample return missions. Additional information is contained within the original extended abstract.

DesMarais, David J.↗

Programmable Pacemaker

Released in 1995, the Trilogy cardiac pacemaker is the fourth generation of a unit developed in the 1970s by NASA, Johns Hopkins Applied Physics Laboratory and St. Jude Medical's Cardiac Rhythm Management Division (formerly known as Pacesetter Systems, Inc.). The new system incorporates the company's PDx diagnostic and programming software and a powerful microprocessor that allows more functions to be fully automatic and gives more detailed information on the patient's health and the performance of the pacing systems. The pacemaker incorporates bidirectional telemetry used for space communications for noninvasive communication with the implanted pacemaker, smaller implantable pulse generators from space microminiaturization, and longer-life batteries from technology for spacecraft electrical power systems.

Source record↗

High altitude subsonic parachute field programmable gate array

This paper describes a rapid, top down requirements-driven design of an FPGA used in an Earth qualification test program for a new Mars subsonic parachute. The FPGA is used to process and control storage of telemetry data from multiple sensors throughout; launch, ascent, deployment and descent phases of the subsonic parachute test.

FPGA methodology↗

Programmable noise bandwidth reduction by means of digital averaging

Predetection noise bandwidth reduction is effected by a pre-averager capable of digitally averaging the samples of an input data signal over two or more symbols, the averaging interval being defined by the input sampling rate divided by the output sampling rate. As the averaged sample is clocked to a suitable detector at a much slower rate than the input signal sampling rate the noise bandwidth at the input to the detector is reduced, the input to the detector having an improved signal to noise ratio as a result of the averaging process, and the rate at which such subsequent processing must operate is correspondingly reduced. The pre-averager forms a data filter having an output sampling rate of one sample per symbol of received data. More specifically, selected ones of a plurality of samples accumulated over two or more symbol intervals are output in response to clock signals at a rate of one sample per symbol interval. The pre-averager includes circuitry for weighting digitized signal samples using stored finite impulse response (FIR) filter coefficients. A method according to the present invention is also disclosed.

Poklemba, John J.↗

Programmable DMA controller

In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.

Hendry, David F.↗

Electronic processing and control system with programmable hardware

A computer system with reprogrammable hardware allowing dynamically allocating hardware resources for different functions and adaptability for different processors and different operating platforms. All hardware resources are physically partitioned into system-user hardware and application-user hardware depending on the specific operation requirements. A reprogrammable interface preferably interconnects the system-user hardware and application-user hardware.

Alkalaj, Leon↗

Integrated sensor with frame memory and programmable resolution for light adaptive imaging

An image sensor operable to vary the output spatial resolution according to a received light level while maintaining a desired signal-to-noise ratio. Signals from neighboring pixels in a pixel patch with an adjustable size are added to increase both the image brightness and signal-to-noise ratio. One embodiment comprises a sensor array for receiving input signals, a frame memory array for temporarily storing a full frame, and an array of self-calibration column integrators for uniform column-parallel signal summation. The column integrators are capable of substantially canceling fixed pattern noise.

Zhou, Zhimin↗