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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 523 records · Page 29
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Experimental Examination of Additively Manufactured Patterns on Structural Nuclear Materials for Digital Image Correlation Strain Measurements

Abstract Background There are a limited number of commercially available sensors for monitoring the deformation of materials in-situ during harsh environment applications, such as those found in the nuclear and aerospace industries. Such sensing devices, including weldable strain gauges, extensometers, and linear variable differential transformers, can be destructive to material surfaces being investigated and typically require relatively large surface areas to attach (> 10 mm in length). Digital image correlation (DIC) is a viable, non-contact alternative to in-situ strain deformation. However, it often requires implementing artificial patterns using splattering techniques, which are difficult to reproduce. Objective Additive manufacturing capabilities offer consistent patterns using programmable fabrication methods. Methods In this work, a variety of small-scale periodic patterns with different geometries were printed directly on structural nuclear materials (i.e., stainless steel and aluminum tensile specimens) using an aerosol jet printer (AJP). Unlike other additive manufacturing techniques, AJP offers the advantage of materials selection. DIC was used to track and correlate strain to alternative measurement methods during cyclic loading, and tensile tests (up to 1100 µɛ) at room temperature. Results The results confirmed AJP has better control of pattern parameters for small fields of view and facilitate the ability of DIC algorithms to adequately process patterns with periodicity. More specifically, the printed 100 μm spaced dot and 150 μm spaced line patterns provided accurate measurements with a maximum error of less than 2% and 4% on aluminum samples when compared to an extensometer and commercially available strain gauges. Conclusion Our results highlight a new pattern fabrication technique that is form factor friendly for digital image correlation in nuclear applications.

Novich, K. A. (ORCID:0000000204466022)↗
DOE OSTI2017

Unattended Dual Current Monitor (UDCM) FY17 Summary Report

The UDCM is a low current measurement device designed to record pico-amp to micro-amp currents from radiation detectors. The UDCM is the planned replacement for the IAEA’s obsolete MiniGRAND data acquisition module. Preliminary testing of the UDCM at the IAEA facilities lead to the following recommendations from the IAEA: Increase the measurement range. Lower range by a factor of 5 and upper range by 2 orders of magnitude; Modifications to the web interface; Increase programmable acquisition time to 3600s; Develop a method to handle current offsets and negative current; Error checking when writing data to the uSD card; and Writing BID files along with the currently stored BI0 files.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2013

An Offload NIC for NASA, NLR, and Grid Computing

This work addresses distributed data management and access dynamically configurable high-speed access to data distributed and shared over wide-area high-speed network environments. An offload engine NIC (network interface card) is proposed that scales at nX10-Gbps increments through 100-Gbps full duplex. The Globus de facto standard was used in projects requiring secure, robust, high-speed bulk data transport. Novel extension mechanisms were derived that will combine these technologies for use by GridFTP, bandwidth management resources, and host CPU (central processing unit) acceleration. The result will be wire-rate encrypted Globus grid data transactions through offload for splintering, encryption, and compression. As the need for greater network bandwidth increases, there is an inherent need for faster CPUs. The best way to accelerate CPUs is through a network acceleration engine. Grid computing data transfers for the Globus tool set did not have wire-rate encryption or compression. Existing technology cannot keep pace with the greater bandwidths of backplane and network connections. Present offload engines with ports to Ethernet are 32 to 40 Gbps f-d at best. The best of ultra-high-speed offload engines use expensive ASICs (application specific integrated circuits) or NPUs (network processing units). The present state of the art also includes bonding and the use of multiple NICs that are also in the planning stages for future portability to ASICs and software to accommodate data rates at 100 Gbps. The remaining industry solutions are for carrier-grade equipment manufacturers, with costly line cards having multiples of 10-Gbps ports, or 100-Gbps ports such as CFP modules that interface to costly ASICs and related circuitry. All of the existing solutions vary in configuration based on requirements of the host, motherboard, or carriergrade equipment. The purpose of the innovation is to eliminate data bottlenecks within cluster, grid, and cloud computing systems, and to add several more capabilities while reducing space consumption and cost. Provisions were designed for interoperability with systems used in the NASA HEC (High-End Computing) program. The new acceleration engine consists of state-ofthe- art FPGA (field-programmable gate array) core IP, C, and Verilog code; novel communication protocol; and extensions to the Globus structure. The engine provides the functions of network acceleration, encryption, compression, packet-ordering, and security added to Globus grid or for cloud data transfer. This system is scalable in nX10-Gbps increments through 100-Gbps f-d. It can be interfaced to industry-standard system-side or network-side devices or core IP in increments of 10 GigE, scaling to provide IEEE 40/100 GigE compliance.

Awrach, James↗
DOE OSTI2025

Leveraging dendritic complexity for neuromorphic computing

Abstract Beyond-von Neumann computing approaches are necessary to sustain the growth of microelectronics and the increasing appetite for artificial intelligence/machine learning algorithms. Neuromorphic computing is an emerging paradigm that takes inspiration from the brain to provide a path forward to improve the computational efficiency and computational density of next-generation computing architectures. In nature, we observe brains performing complex computations with a much smaller energy footprint than conventional computing approaches. Current neuromorphic systems are focused primarily on scalability, namely, increasing the number of computational units (neurons) and connections between units (synapses). However, for brain-like cognition and efficiency in next-generation computing hardware, we need increased complexity in function, as well as improved connection density for scalability. Here, we present our work that aims to incorporate dendrites for ‘compute-on-wire’ in neuromorphic architectures to increase the computational complexity (e.g. number of programmable parameters, nonlinear dynamics) as well as computational efficiency (energy/compute) of artificial neural networks (ANNs). We do this by showcasing neuromorphic dendrite elements that can be leveraged for various applications. We will present examples of neuroscience-inspired direction-selective circuits and an ANN with active dendrites leveraging shunting inhibition. We also demonstrate the benefits of using dendrites in deep neural networks. To conclude, we discuss how we can utilize emerging hardware devices in these systems and design next-generation neuromorphic architectures with dendrites.

Cardwell, Suma G. (ORCID:0000000226575545)↗
NASA NTRS2014

SpaceCube v2.0 Space Flight Hybrid Reconfigurable Data Processing System

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.

Xilinx FPGA↗
DOE OSTI2023

2D Exotic Optical Lattice via a Digital‐Coding Circular Airy Beam

Optical lattices have been widely used from classical to quantum physics. The tunable and scalable fabrication of lattices would be of great significance in lattice‐based multipartite applications. This work demonstrates first that a circular Airy beam (CAB), which has the peculiar properties of self‐healing and abrupt autofocusing, can be used to generate two‐dimensional (2D) optical lattices in propagation when encoded by a programmable spatial mask, resulting in the formation of large‐scale and tunable optical lattices with both axis and axial symmetry, and even high‐orbital kaleidoscope shapes. The efficient diffraction of CAB during the spatial crosstalk with the mask enables the realization of tunable lattices with rich periodicity and complexity. The study shows a flexible method to manipulate lattices with large‐scale and versatile structures for potential applications in integrated and scalable optical and photonic devices.

Sun, Peisheng↗
DOE OSTI2021

PLC-based Impedance Measurement and Current Injection Response Analysis

Studying and mitigating the vulnerabilities of Programmable Logic Controllers (PLCs) to electromagnetic pulse is important for the reliability of the power system. In this paper, an effective impedance measurement scheme is proposed to estimate the susceptibility of PLCs to an electromagnetic pulse. The equivalent non-uniform transmission line model is established to eliminate the impact of the fixture in the de-embedding process. Based on the measured impedance, the equivalent circuit is established to calculate the response of the device when subjected to the electromagnetic pulse. The voltage and current responses of different interfaces are compared utilizing the developed pulse Current Injection (CI) method. Finally, the impedance measurement scheme is verified through testing using three measuring instruments. And the CI simulation experiments reveal the characteristics and susceptibilities of different PLCs interfaces, indicating that some protection measures are required for the reliable operation of PLC.

Qiu, Wei↗
NASA NTRS1994

A programmable heater control circuit for spacecraft

Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

Nguyen, D. D.↗
NASA NTRS2016

Single Event Effects in FPGA Devices 2015-2016

This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

Xilinx V5↗
DOE OSTI2024

Alumina–Titania Nanolaminate Condensers for Hot Programmable Catalysis

Nanolaminates composed of thin alternating layers of Al2O 3 and TiO 2 (ATO) were engineered by using atomic layer deposition as the dielectric material for a Pt-on-carbon catalytic condenser. Investigation assessed synthesis parameters including the deposition temperature, Al 2 O 3 and TiO 2 layer thicknesses, total number of layers, and a capping Al 2 O 3 layer on the maximum charge accumulation in the Pt catalyst. The highest capacitance ATO configuration demonstrated a specific capacitance of ∼1200 nF/cm 2 with working voltages of ±5 V, enabling the storage of 4 × 10 13 electrons or holes per cm 2 at room temperature. The ATO devices exhibited enhanced capacitance at elevated temperatures of up to 400 °C, suggesting the suitability of these materials for high-temperature applications. Adsorption of carbon monoxide on the Pt/C-ATO device characterized by grazing incidence infrared spectroscopy showed changes in the surface binding energy of 13.1 ± 0.8 kJ/mol for an applied external voltage bias of ±1 V.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1995

Sensor Systems for Space Life Sciences

Sensors 2000! (S2K!) is a NASA Ames Research Center engineering initiative designed to provide biosensor and bio-instrumentation systems technology expertise to NASA's life sciences spaceflight programs. S2K! covers the full spectrum of sensor technology applications, ranging from spaceflight hardware design and fabrication to advanced technology development, transfer and commercialization. S2K! is currently developing sensor systems for space biomedical applications on BION (a Russian biosatellite focused on Rhesus Monkey physiology) and NEUROLAB (a Space Shuttle flight devoted to neuroscience). It's Advanced Technology Development-Biosensors (ATD-B) project focuses efforts in five principle areas: biotelemetry Systems, chemical and biological sensors, physiological sensors, advanced instrumentation architectures, and data and information management. Technologies already developed and tested included, application-specific sensors, preamplifier hybrids, modular programmable signal conditioners, power conditioning and distribution systems, and a fully implantable dual channel biotelemeter. Systems currently under development include a portable receiver system compatible with an off-the-shelf analog biotelemeter, a 4 channel digital biotelemetry system which monitors pH, a multichannel, g-processor based PCM biotelemetry system, and hand-held personal monitoring systems. S2K! technology easily lends itself to telescience and telemedicine applications as a front-end measurement and data acquisition device, suitable for obtaining and configuring physiological information, and processing that information under control from a remote location.

Somps, Chris J.↗
NASA NTRS2004

Enhancements to a Superconducting Quantum Interference Device (SQUID) Multiplexer Readout and Control System

Far-infrared detector arrays such as the 16x32 superconducting bolometer array for the SAFIRE instrument (flying on the SOFIA airborne observatory) require systems of readout and control electronics to provide translation between a user-driven, digital PC and the cold, analog world of the cryogenic detector. In 2001, the National Institute of Standards and Technology (NIST) developed their Mark III electronics for purposes of control and readout of their 1x32 SQUID Multiplexer chips. We at NASA s Goddard Space Flight Center acquired a Mark 111 system and subsequently designed upgrades to suit our and our collaborators purposes. We developed an arbitrary, programmable multiplexing system that allows the user to cycle through rows in a SQUID array in an infinite number of combinations. We provided hooks in the Mark III system to allow readout of signals from outside the Mark 111 system, such as telescope status information. Finally, we augmented the heart of the system with a new feedback algorithm implementation, flexible diagnostic tools, and informative telemetry.

Forgione, J.↗
NASA NTRS1998

Refurbishment and Automation of the Thermal/Vacuum Facilities at the Goddard Space Flight Center

The thermal/vacuum facilities located at the Goddard Space Flight Center (GSFC) have supported both manned and unmanned space flight since the 1960s. Of the 11 facilities, currently 10 of the systems are scheduled for refurbishment and/or replacement as part of a 5-year implementation. Expected return on investment includes the reduction in test schedules, improvements in the safety of facility operations, reduction in the complexity of a test and the reduction in personnel support required for a test. Additionally, GSFC will become a global resource renowned for expertise in thermal engineering, mechanical engineering and for the automation of thermal/vacuum facilities and thermal/vacuum tests. Automation of the thermal/vacuum facilities includes the utilization of Programmable Logic Controllers (PLCs) and the use of Supervisory Control and Data Acquisition (SCADA) systems. These components allow the computer control and automation of mechanical components such as valves and pumps. In some cases, the chamber and chamber shroud require complete replacement while others require only mechanical component retrofit or replacement. The project of refurbishment and automation began in 1996 and has resulted in the computer control of one Facility (Facility #225) and the integration of electronically controlled devices and PLCs within several other facilities. Facility 225 has been successfully controlled by PLC and SCADA for over one year. Insignificant anomalies have occurred and were resolved with minimal impact to testing and operations. The amount of work remaining to be performed will occur over the next four to five years. Fiscal year 1998 includes the complete refurbishment of one facility, computer control of the thermal systems in two facilities, implementation of SCADA and PLC systems to support multiple facilities and the implementation of a Database server to allow efficient test management and data analysis.

Donohue, John T.↗
NASA NTRS1995

Prototype Focal-Plane-Array Optoelectronic Image Processor

Prototype very-large-scale integrated (VLSI) planar array of optoelectronic processing elements combines speed of optical input and output with flexibility of reconfiguration (programmability) of electronic processing medium. Basic concept of processor described in "Optical-Input, Optical-Output Morphological Processor" (NPO-18174). Performs binary operations on binary (black and white) images. Each processing element corresponds to one picture element of image and located at that picture element. Includes input-plane photodetector in form of parasitic phototransistor part of processing circuit. Output of each processing circuit used to modulate one picture element in output-plane liquid-crystal display device. Intended to implement morphological processing algorithms that transform image into set of features suitable for high-level processing; e.g., recognition.

Fang, Wai-Chi↗
NASA NTRS2006

Microshutter Arrays for the JWST NIRSpec

A primary goal of the James Webb Space Telescope (JWST) is to characterize the birth and evolution of galaxies by imaging and spectroscopic observations. The telescope will use a Near Infrared Camera and a Near Infrared Spectrometer (NIRSpec) to carry out this program. The 3.6 x 3.6 field of NIRSpec will contain thousands of candidate high redshift galaxies. With such a high candidate object density, simultaneous multi-object capability is essential. This capability requires a programmable object selection mask to eliminate sky background and to reduce source confusion caused. We are developing a two-dimensional programmable field mask for NIRSpec. These masks employ micromechanical (MEMS) techniques to provide source selection over the NIRSpec field of view. The first flight format arrays (171x365 shutters) have been fabricated and full functionality of these arrays has been demonstrated in lab tests. Qualification tests are in progress to demonstrate readiness for flight, and will be complete in the early fall of 2006. In this paper, I describe performance of this critical new technology, and progress in making the devices ready for a 2008 delivery to ESA for inclusion in the NIRSpec.

Moseley, Samuel H.↗
NASA NTRS2009

FPGA-Based Networked Phasemeter for a Heterodyne Interferometer

A document discusses a component of a laser metrology system designed to measure displacements along the line of sight with precision on the order of a tenth the diameter of an atom. This component, the phasemeter, measures the relative phase of two electrical signals and transfers that information to a computer. Because the metrology system measures the differences between two optical paths, the phasemeter has two inputs, called measure and reference. The reference signal is nominally a perfect square wave with a 50- percent duty cycle (though only rising edges are used). As the metrology system detects motion, the difference between the reference and measure signal phases is proportional to the displacement of the motion. The phasemeter, therefore, counts the elapsed time between rising edges in the two signals, and converts the time into an estimate of phase delay. The hardware consists of a circuit board that plugs into a COTS (commercial, off-the- shelf) Spartan-III FPGA (field-programmable gate array) evaluation board. It has two BNC inputs, (reference and measure), a CMOS logic chip to buffer the inputs, and an Ethernet jack for transmitting reduced-data to a PC. Two extra BNC connectors can be attached for future expandability, such as external synchronization. Each phasemeter handles one metrology channel. A bank of six phasemeters (and two zero-crossing detector cards) with an Ethernet switch can monitor the rigid body motion of an object. This device is smaller and cheaper than existing zero-crossing phasemeters. Also, because it uses Ethernet for communication with a computer, instead of a VME bridge, it is much easier to use. The phasemeter is a key part of the Precision Deployable Apertures and Structures strategic R&D effort to design large, deployable, segmented space telescopes.

Rao, Shanti↗
NASA NTRS2010

Modeling of Sonos Memory Cell Erase Cycle

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

Phillips, Thomas A.↗
DOE OSTI2022

Heterosynaptic plasticity in biomembrane memristors controlled by pH

Abstract In biology, heterosynaptic plasticity maintains homeostasis in synaptic inputs during associative learning and memory, and initiates long-term changes in synaptic strengths that nonspecifically modulate different synapse types. In bioinspired neuromorphic circuits, heterosynaptic plasticity may be used to extend the functionality of two-terminal, biomimetic memristors. In this article, we explore how changes in the pH of droplet interface bilayer aqueous solutions modulate the memristive responses of a lipid bilayer membrane in the pH range 4.97–7.40. Surprisingly, we did not find conclusive evidence for pH-dependent shifts in the voltage thresholds ( V* ) needed for alamethicin ion channel formation in the membrane. However, we did observe a clear modulation in the dynamics of pore formation with pH in time-dependent, pulsed voltage experiments. Moreover, at the same voltage, lowering the pH resulted in higher steady-state currents because of increased numbers of conductive peptide ion channels in the membrane. This was due to increased partitioning of alamethicin monomers into the membrane at pH 4.97, which is below the pKa (~5.3–5.7) of carboxylate groups on the glutamate residues of the peptide, making the monomers more hydrophobic. Neutralization of the negative charges on these residues, under acidic conditions, increased the concentration of peptide monomers in the membrane, shifting the equilibrium concentrations of peptide aggregate assemblies in the membrane to favor greater numbers of larger, increasingly more conductive pores. It also increased the relaxation time constants for pore formation and decay, and enhanced short-term facilitation and depression of the switching characteristics of the device. Modulating these thresholds globally and independently of alamethicin concentration and applied voltage will enable the assembly of neuromorphic computational circuitry with enhanced functionality. Impact statement We describe how to use pH as a modulatory “interneuron” that changes the voltage-dependent memristance of alamethicin ion channels in lipid bilayers by changing the structure and dynamical properties of the bilayer. Having the ability to independently control the threshold levels for pore conduction from voltage or ion channel concentration enables additional levels of programmability in a neuromorphic system. In this article, we note that barriers to conduction from membrane-bound ion channels can be lowered by reducing solution pH, resulting in higher currents, and enhanced short-term learning behavior in the form of paired-pulse facilitation. Tuning threshold values with environmental variables, such as pH, provide additional training and learning algorithms that can be used to elicit complex functionality within spiking neural networks. Graphical abstract

36 MATERIALS SCIENCE↗