Results for “ADC” — Page 3

DOE OSTI2024

Machine Learning for DUNE Supernova Trigger

One of the major scientific goals of the Deep Underground Neutrino Experiment (DUNE) is to detect and measure the neutrino flux from galactic core-collapse supernovae. These neutrinos, which exist in the low energy range of up to a few tens of MeV and are responsible for carrying away over 99% of the gravitational binding energy of the supernova, provide an opportunity to study the end of life evolution of massive stars, as well as unique properties and interactions of neutrinos. Because galactic supernovae are expected to occur only on the timespan of every few decades, it is crucial that DUNE is able to detect supernova neutrino interactions when they occur. However, detecting these supernova interactions requires sifting through a large amount of data, and DUNE detectors require a trigger to signal when supernova neutrino events occur. Machine learning provides a potential approach to creating this trigger. This project generates ADC and ground truth images of neutrino interactions in a LArTPC detector as simulated by the Model of Argon Reaction Low Energy Yields (MARLEY) to be used for machine learning. The eventual goal of this work is to facilitate DUNE s detection of supernova neutrino interactions by building a machine learning pipeline that will train the trigger algorithm.

Damish, Stephanie↗

DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗

DOE OSTI2024

Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. This effort is pursuing the co-design development of high-performance readout smart pixel ASICs for a future Phase III High Luminosity upgrade of the Large Hadron Collider. A 1.6mm2 ASIC prototype was designed by Fermilab in CMOS 28 nm bulk process and submitted for manufacturing in February 2024. It leverages the analog front-end pixel design of a previous prototype fabricated and tested in 2023, which achieved a simulated detection level of ~400e- with 30fF input capacitance. The ROIC consists of two matrices of 16×16 smart pixels, each 25×25 μm2 in size. Each smart pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. There is digital space for the integration of our fully combinatorial AI that performs momentum classification at the bunch crossing rate. The total power consumption is ∼6μW per pixel, which corresponds to ~1mW/cm2. The ASIC incorporates programmable front-end charge injection circuitry to generate pixel cluster charges during characterization. The cluster profile will be generated to duplicate hit characteristics of various momentum (pT). We will present early results from chip testing.

Parpillon, Benjamin↗

DOE OSTI2025

Performance and automatic calibration scheme of the waveform sampler in the ETROC2 ASIC chip

The waveform sampler in the CMS ETROC2 chip for LGAD gain aging monitoring is a 2.56-GS/s 12-bit 8x-Interleaved ADC that consists of a coarse SAR stage, and a fine stage. This architecture delivers high performance on a relatively modest 65 nm process, while requires finding up to 24 calibration constants through calibration. We developed an automatic calibration method using charge injection test data. After calibration, the baseline random error is reduced by a factor of 2.5–3 compared to the default calibration, and a 5% charge measurement precision is achieved in 15 fC charge injection tests.

Fu, Tao [Unlisted, US]↗

DOE OSTI2026

Apex Study: Compensating Transient Beam Loading in the RHIC 28 MHZ

With the EIC on the way, it is important that developments and strategies are in place to deal with the very high beam currents that the machine will feature. Specifically, the EIC will collide beams of up to 2.5 A, three times the beam current in RHIC. This higher beam current will cause significant voltage transients in the cavity fields which can lead to longitudinal instabilities and beam loss. In anticipation of these negative effects, studies were carried out on the RHIC 28 MHz cavities using newly developed firmware and software to diagnose and combat beam loading. Diagnostic tools such as the bunch-by-bunch (BbyB) ADC firmware and digital network analyzer (DNA) were used to characterize the closed loop system and transient on the cavity voltage magnitude and phase. Then, a one-turn delay feedback (OTFB) and adaptive feed-forward (aFFWD) were used to minimize the transient beam loading. The studies were carried out with beam during 2 accelerator physics experiements (APEXs) using one of the 28 MHz accelerating cavities here at RHIC.

43 PARTICLE ACCELERATORS↗

DOE OSTI2025

Development of BPM Electronics for PIP-II at Fermilab

This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability is validated through dedicated testing.

Liu, Shengli [Fermilab] (ORCID:0009000128436936)↗

DOE OSTI2026

Captan+X Data Converter Integration

Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.

Espinoza, David [Illinois U., Urbana (main)]↗

DOE OSTI2026

Short Circuit Detection and Voltage Sense for High Voltage Ionization Tube Power Supplies

Fermilab's PIP-II upgrade requires new rack-mounted power supplies for Beam Loss Monitor (BLM) ionization tubes compatible with the microTCA 4.1 standard, supporting high-side current measurement for short circuit detection, voltage sense telemetry, and low-side current measurement for beam loss readout. This work presents the design and preliminary schematic of such a supply. A resistive current sensing approach was chosen over inductive, optical, and Hall-effect alternatives for its independence from cable length and component availability. A 500 mΩ inline shunt steps the 2 kV common mode voltage down to roughly 70 V, producing a ~27 μV pulse during a short, which is amplified 500x, compared against a 14-bit DAC threshold, and latched to drive a fault line. Voltage sense steps the 2 kV output down at a 1V/1000V ratio, buffers it with a low bias current amplifier, and digitizes it via a 24-bit ADC over SPI. Onboard power is regulated from 12 V down to isolated 5 V and 3.3 V rails, with capacitive isolation on FPGA communication lines. Lumped parameter models were developed for the ionization tube (0.327 nF, 20 to 200 GΩ dynamic resistance) and the RG-58 coaxial cable to support the design. Component selection is complete and a preliminary schematic has been drawn in Altium Designer, forming the foundation for future prototyping and validation.

Yu, Kellen [Cornell U.]↗

DOE OSTI2025

Search for Axions in Magnetic White Dwarf Polarization at Lick and Keck Observatories

We present the most sensitive search to date for light axion-like particles with masses below a micro-eV, using spectropolarimetric data collected from the Lick and Keck Observatories. The conversion of optical photons emitted from the surface of a magnetic white dwarf (MWD) into axions in the strong magnetic field around the star induces a nearly wavelength-independent linear polarization in the observed starlight. We analyze the Stokes parameters $(U, Q, I)$ measured with the Kast spectrograph at the Lick Observatory toward the MWDs SDSS J033320+000720 and ZTF J190132+145807, and with the LRISp-ADC instrument at the Keck Observatory toward ZTF J190132+145807, SDSS J002129+150223, and SDSS J100356+053825 to search for this effect. The data show no evidence of axion-induced linear polarization, and we set world-leading constraints on the axion-photon coupling $|g_{aγγ}| \lesssim 1.7 \times 10^{-12} \,\mathrm{GeV}^{-1}$ at the $95\%$ confidence level for masses $m_a \lesssim 2 \times 10^{-7}\,\mathrm{eV}$.

FOS: Physical sciences↗

DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2024

Machine Learning for DUNE Supernova Trigger

One of the major scientific goals of the Deep Underground Neutrino Experiment (DUNE) is to detect and measure the neutrino flux from galactic core-collapse supernovae. These neutrinos, which exist in the low energy range of up to a few tens of MeV and are responsible for carrying away over 99% of the gravitational binding energy of the supernova, provide an opportunity to study the end of life evolution of massive stars, as well as unique properties and interactions of neutrinos. Because galactic supernovae are expected to occur only on the timespan of every few decades, it is crucial that DUNE is able to detect supernova neutrino interactions when they occur. However, detecting these supernova interactions requires sifting through a large amount of data, and DUNE detectors require a trigger to signal when supernova neutrino events occur. Machine learning provides a potential approach to creating this trigger. This project generates ADC and ground truth images of neutrino interactions in a LArTPC detector as simulated by the Model of Argon Reaction Low Energy Yields (MARLEY) to be used for machine learning. The eventual goal of this work is to facilitate DUNE s detection of supernova neutrino interactions by building a machine learning pipeline to train the trigger algorithm.

Damish, Stephanie↗

DOE OSTI2024

Machine Learning for DUNE Supernova Trigger

One of the major scientific goals of the Deep Underground Neutrino Experiment (DUNE) is to detect and measure the neutrino flux originating from galactic core-collapse supernovae. These neutrinos provide an opportunity to study the end of life evolution of massive stars, and reveal information about the structure of core-collapse that is not visible in observations of the electromagnetic spectrum. Because of the rarity of these events, it is crucial that DUNE is able to detect supernova neutrino interactions when they occur. However, this will require sifting through a large quantity of data, motivating the development of a trigger algorithm to identify significant events and discard irrelevant data. Machine learning provides a potential approach to building this trigger. This project generates ADC and ground truth images of simulated neutrino interactions in a LArTPC detector to be used for machine learning, and uses them to train a sparse Convolutional Neural Network (C NN). The performance of this model when applied to the task of pixel classification based on interaction type is examined. This project found that the sparse CNN approach has the potential to have high accuracy in pixel classification, meaning it may be highly relevant to the development of a supernova neutrino trigger for the DUNE far detector.

Damish, S.↗

DOE OSTI2024

Calibration of the analog beam-signal hardware for the credited engineered beam power limit system at the Proton Power Upgrade Project at the Spallation Neutron Source

A programmable signal processor-based credited safety control that calculates pulsed beam power based on beam kinetic energy and charge was designed as part of the Proton Power Upgrade (PPU) project at the Spallation Neutron Source (SNS). The system must reliably shut off the beam if the average power exceeds 2.145 MW averaging over 60 seconds. System calibration requires pedigree in measurements, calibration setup, and calculations. This paper discusses the calibration of the analog beam signal components up to and including the Analog Digital Convertors (ADCs) for implementation into the Safety Programmable Logic Controllers (PLCs) and Field Programmable Gate Arrays (FPGAs).

Bobrek, Miljko↗

DOE OSTI2025

Development of BPM electronics for PIP-II at Fermilab

This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability - is validated through dedicated testing.

Liu, Shengli [Fermilab] (ORCID:0009000128436936)↗

DOE OSTI2025

Obsidian

Obsidian A35 is a compact FPGA carrier board designed to interface with ADCs, DACs or other devices, either stand-alone or as an I/O expansion board. The connectivity includes 1 GigE, 4 SFP, 6 PMOD, FTDI USB and Arduino shield compatible header. The board features also a FPGA boot SPI Flash, on-chip DDR3 memory, VCXO and White Rabbit compatibility.

Moore, Victoria [Lawrence Berkeley National Labora↗

DOE OSTI2026

CAPTAN+X Data Converter Integration

Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.

Espinoza, David [Illinois U., Urbana (main)]↗

DOE OSTI2026

DLK1 is a GATA1s-driven dependency and therapeutic target in Down syndrome–associated myeloid leukemia

Children with Down syndrome have a markedly increased risk of developing myeloid leukemia. Although having an excellent prognosis, 10% to 20% develop relapsed or refractory disease with poor survival, highlighting the need for new targeted approaches. The pathogenesis of myeloid leukemia of Down syndrome (ML-DS) is tightly linked to fetal hematopoiesis and mutations in GATA1, generating the truncated GATA1 short (GATA1s) isoform. We identified Delta-like noncanonical Notch ligand 1 (DLK1) as a direct GATA1s target. DLK1, a paternally imprinted transmembrane protein, is highly expressed in fetal liver CD34 + cells but absent in adult hematopoiesis, making it an attractive immunotherapeutic target. Chromatin profiling revealed GATA1s occupancy at a distal enhancer within the DLK1-DIO3 locus, driving aberrant DLK1 upregulation in ML-DS. Functional studies demonstrated that DLK1 is a leukemia dependency, as its genetic ablation impaired proliferation and engraftment, induced apoptosis, and altered Notch and β-catenin signaling. Therapeutically, a DLK1-directed antibody-drug conjugate–induced selective cytotoxicity, abrogated colony formation, and significantly prolonged survival in refractory ML-DS patient-derived xenograft (PDX) models, achieving durable remissions at higher doses. These findings establish DLK1 as a leukemia-specific vulnerability and provide preclinical proof-of-concept for DLK1-targeted therapies in ML-DS and other leukemias with fetal-like expression programs.

Biological and medical sciences↗

DOE OSTI2024

Field Programmable Gate Array Data Capture for Control Systems

Some Industrial Control Systems (ICS) networks are based on protocols such as Serial and Industrial Ethernet. These protocols currently have no existing cybersecurity monitoring tools, leaving a large gap in the cyber defense of critical infrastructure. In order to analyze such ICS traffic, it is first necessary to implement methods of capturing the ICS data. Whereas traditional methods of analyzing data would use microprocessors, the nature of high-speed analog data can be difficult to implement on such a versatile processor, as they are rather inefficient for doing a single task. Whereas Field Programmable Gate Arrays (FPGAs) provide an adequate tool in analyzing high speed data, as despite the lack of program versatility, Programmable Logic can implement a solution with minimal clock cycles, allowing time for each new packet of data to be captured before a new data sample is taken.

42 ENGINEERING↗