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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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This paper discusses limitation of each system and provides representative inspection images for CCGA/BGA assemblies.
This paper reports the results of an experiment that utilized the JPL's area array consortium test vehicle design, containing a myriad of mixed technology components with an OSP finish. The details of the reliability study are presented in this paper.
System in a package (SIP) development is a response to an increasing demand for integration of different functions into one unit to reduce size and cost and improve functionality. Qualification of the newly developed multifunctional electronics are becoming complex at the package level and even more at the second and system levels.
A JPL-led chip scale package consortium of enterprises recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages for a variety of projects. The experience of the consortium in building more than 150 test vehicle assemblies, single and double sided multilayer PWBs, and the environmental test results has now been published as a chip scale package guidelines document.
This paper presents the effects of paste printing parameters including stencil thickness, squeegee length and materials, and pressurized head on solder paste volume.
Package/die stacking technology enhances most aspects of electronic systems such as size, weight, speed, yield, and power consumption.
In this paper, the assembly process flow, solder paste for different stencil design, manufacturing defects, X-ray inspection results, and ultrasonic characterizations are reported.
The popularity of emerging miniaturized Chip Scale Packages (CSPs) is rapidly growing because of their benefits and smaller size, though they may be considered to be an interim solution.
This paper will present cycles to failure in Weibull plots as well as their failure characteristics up to 7000 cycles.
(view graphs) QA Proactive Approach, SM Package Trends, Introduction on Ball Grid Array, Environmental Test.
The Jet Propulsion Laboratory (JPL) is currently assessing the use of Ball Grid Arrays (BGAs) for National Aeronautics and Space Administration (NASA) spaceflight applications. This work is being funded through NASA Headquarters, Code Q. The objectives are to demonstrate the robustness, quality and reliability of BGAs technology, and to assist in the solicited industrial, academic and other related consortia to work together to leverage the related efforts into a synergistic effort. Initial results of these activities will be summarized and presented in this paper.
Team members representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
This paper will present failure characteristics of the assemblies up to 7,000 cycles.
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Area array packages (AAPs) with 1.27 mm pitch have been the packages of choice for commercial applications; they are now starting to be implemented for use in military and aerospace applications. Thermal cycling characteristics of plastic ball grid array (PBGA) and chip scale package assemblies, because of their wide usage for commercial applications, have been extensively reported on in literature. Thermal cycling represents the on-off environmental condition for most electronic products and therefore is a key factor that defines reliability.However, very limited data is available for thermal cycling behavior of ceramic packages commonly used for the aerospace applications. For high reliability applications, numerous AAPs are available with an identical design pattern both in ceramic and plastic packages. This paper compares assembly reliability of ceramic and plastic packages with the identical inputs/outputs(I/Os) and pattern. The ceramic package was in the form of ceramic column grid array (CCGA) with 560 I/Os peripheral array with the identical pad design as its plastic counterpart.
No abstract available
Single-Event Effects (SEE) testing was conducted on the AMD Ryzen 3 1200 microprocessor. Testing was conducted at Massachusetts General Hospital's (MGH) Francis H. Burr Proton Therapy Center on June 2nd, 2019.
Single-Event Effects (SEE) testing was conducted on the AMD Ryzen 3 2200G microprocessor with integrated graphics. Testing was conducted at Massachusetts General Hospital's (MGH) Francis H. Burr Proton Therapy Center on June 2nd, 2019.