Organic Relay Carry Generator and Logic Gates
Our letter demonstrates that a single organic micrometer-scale relay can easily generate a carry for four input bits and perform basic Boolean operations for two input bits.
42 ENGINEERING↗
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Machine Learning–Guided Boolean Matrix Inference for Real-Time O-RAN Conflict Detection
Open Radio Access Networks (O-RAN) are emerging, software-driven cellular architectures that promote flexibility by enabling components from different vendors to interoperate. Multiple control applications called xApps can independently adjust network parameters in near real time, often without awareness of each other's actions. This creates a system highly prone to unintended conflicts and performance degradation due to the inherent complexity of such openness. To model such systems and ultimately prevent or mitigate xApp conflicts, it is essential to understand the dynamic relationships between xApps (A), the control parameters they adjust (P), and the resulting KPI responses (K). While the mappings from A to P and from K to A can often be derived from xApp specifications, the relationship from P to K is typically hidden within the system’s dynamics and must be inferred from observed data. We propose a novel data-driven Boolean inference framework that uncovers the hidden P?K dependencies using machine learning and interpretable rule induction. Continuous parameters and KPIs are first binarized using decision tree classifiers, and a binary influence matrix L is then inferred by solving Boolean matrix equations over time. This compact representation improves interpretability and enables real-time tracking of dynamically evolving parameter-KPI dependencies. We demonstrate the effectiveness of our method in a realistic mobile handover scenario, where it accurately recovers the underlying logic and enables proactive conflict detection.
42 - ENGINEERING↗
Revisiting separation: Algorithms and complexity
Abstract Linear temporal logic (LTL) with Since and Until modalities is expressively equivalent, over the class of complete linear orders, to a fragment of first-order logic known as FOMLO (first-order monadic logic of order). It turns out that LTL, under some basic assumptions, is expressively complete if and only if it has the property, called separation, that every formula is equivalent to a Boolean combination of formulas that each refer only to the past, present or future. Herein we present simple algorithms and their implementations to perform separation of the LTL with Since and Until, over discrete and complete linear orders, and translation from FOMLO formulas into equivalent temporal logic formulas. We additionally show that the separation of a certain fragment of LTL results in at most a double exponential size growth.
Oliveira, Daniel↗
Additively manufacturable micro-mechanical logic gates
Early examples of computers were almost exclusively based on mechanical devices. Although electronic computers became dominant in the past 60 years, recent advancements in three-dimensional micro-additive manufacturing technology provide new fabrication techniques for complex microstructures which have rekindled research interest in mechanical computations. Here we propose a new digital mechanical computation approach based on additively-manufacturable micro-mechanical logic gates. The proposed mechanical logic gates (i.e., NOT, AND, OR, NAND, and NOR gates) utilize multi-stable micro-flexures that buckle to perform Boolean computations based purely on mechanical forces and displacements with no electronic components. A key benefit of the proposed approach is that such systems can be additively fabricated as embedded parts of microarchitected metamaterials that are capable of interacting mechanically with their surrounding environment while processing and storing digital data internally without requiring electric power.
36 MATERIALS SCIENCE↗
Data Analysis
Analysis of the material protection, control, and accountability (MPC&A) system is necessary to understand the limits and vulnerabilities of the system to internal threats. A self-appraisal helps the facility be prepared to respond to internal threats and reduce the risk of theft or diversion of nuclear material. The material control and accountability (MC&A) system effectiveness tool (MSET) fault tree was developed to depict the failure of the MPC&A system as a result of poor practices and random failures in the MC&A system. It can also be employed as a basis for assessing deliberate threats against a facility. MSET uses fault tree analysis, which is a top-down approach to examining system failure. The analysis starts with identifying a potential undesirable event called a 'top event' and then determining the ways it can occur (e.g., 'Fail To Maintain Nuclear Materials Under The Purview Of The MC&A System'). The analysis proceeds by determining how the top event can be caused by individual or combined lower level faults or failures. These faults, which are the causes of the top event, are 'connected' through logic gates. The MSET model uses AND-gates and OR-gates and propagates the effect of event failure using Boolean algebra. To enable the fault tree analysis calculations, the basic events in the fault tree are populated with probability risk values derived by conversion of questionnaire data to numeric values. The basic events are treated as independent variables. This assumption affects the Boolean algebraic calculations used to calculate results. All the necessary calculations are built into the fault tree codes, but it is often useful to estimate the probabilities manually as a check on code functioning. The probability of failure of a given basic event is the probability that the basic event primary question fails to meet the performance metric for that question. The failure probability is related to how well the facility performs the task identified in that basic event over time (not just one performance or exercise). Fault tree calculations provide a failure probability for the top event in the fault tree. The basic fault tree calculations establish a baseline relative risk value for the system. This probability depicts relative risk, not absolute risk. Subsequent calculations are made to evaluate the change in relative risk that would occur if system performance is improved or degraded. During the development effort of MSET, the fault tree analysis program used was SAPHIRE. SAPHIRE is an acronym for 'Systems Analysis Programs for Hands-on Integrated Reliability Evaluations.' Version 1 of the SAPHIRE code was sponsored by the Nuclear Regulatory Commission in 1987 as an innovative way to draw, edit, and analyze graphical fault trees primarily for safe operation of nuclear power reactors. When the fault tree calculations are performed, the fault tree analysis program will produce several reports that can be used to analyze the MPC&A system. SAPHIRE produces reports showing risk importance factors for all basic events in the operational MC&A system. The risk importance information is used to examine the potential impacts when performance of certain basic events increases or decreases. The initial results produced by the SAPHIRE program are considered relative risk values. None of the results can be interpreted as absolute risk values since the basic event probability values represent estimates of risk associated with the performance of MPC&A tasks throughout the material balance area (MBA). The RRR for a basic event represents the decrease in total system risk that would result from improvement of that one event to a perfect performance level. Improvement of the basic event with the greatest RRR value produces a greater decrease in total system risk than improvement of any other basic event. Basic events with the greatest potential for system risk reduction are assigned performance improvement values, and new fault tree calculations show the improvement in total system risk. The operational impact or cost-effectiveness from implementing the performance improvements can then be evaluated. The improvements being evaluated can be system performance improvements, or they can be potential, or actual, upgrades to the system. The RIR for a basic event represents the increase in total system risk that would result from failure of that one event. Failure of the basic event with the greatest RIR value produces a greater increase in total system risk than failure of any other basic event. Basic events with the greatest potential for system risk increase are assigned failure performance values, and new fault tree calculations show the increase in total system risk. This evaluation shows the importance of preventing performance degradation of the basic events. SAPHIRE identifies combinations of basic events where concurrent failure of the events results in failure of the top event.
29 ENERGY PLANNING, POLICY, AND ECONOMY↗
Superior model for fault tolerance computation in designing nano-sized circuit systems
As CMOS technology scales nano-metrically, reliability turns out to be a decisive subject in the design methodology of nano-sized circuit systems. As a result, several computational approaches have been developed to compute and evaluate reliability of desired nano-electronic circuits. The process of computing reliability becomes very troublesome and time consuming as the computational complexity build ups with the desired circuit size. Therefore, being able to measure reliability instantly and superiorly is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into the development of an automated reliability evaluation tool based on the generalization of Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) models. The Matlab-based tool allows users to significantly speed-up the task of reliability analysis for very large number of nano-electronic circuits. Secondly, by using the developed automated tool, the paper explores into a comparative study involving reliability computation and evaluation by PGM and, BDEC models for different implementations of same functionality circuits. Based on the reliability analysis, BDEC gives exact and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, reliability measure by BDEC tends to be lower than the reliability measure by PGM. The lesser reliability measure by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC depends not only on faulty gates but it also depends on circuit topology, probability of input signals being one or zero and also probability of error on signal lines.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Atomic effect algebras with compression bases
Compression base effect algebras were recently introduced by Gudder [Demonstr. Math. 39, 43 (2006)]. They generalize sequential effect algebras [Rep. Math. Phys. 49, 87 (2002)] and compressible effect algebras [Rep. Math. Phys. 54, 93 (2004)]. The present paper focuses on atomic compression base effect algebras and the consequences of atoms being foci (so-called projections) of the compressions in the compression base. Part of our work generalizes results obtained in atomic sequential effect algebras by Tkadlec [Int. J. Theor. Phys. 47, 185 (2008)]. The notion of projection-atomicity is introduced and studied, and several conditions that force a compression base effect algebra or the set of its projections to be Boolean are found. Finally, we apply some of these results to sequential effect algebras and strengthen a previously established result concerning a sufficient condition for them to be Boolean.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Geometric Structure and Transversal Logic of Quantum Reed–Muller Codes
Designing efficient and noise-tolerant quantum computation protocols generally begins with an understanding of quantum error-correcting codes and their native logical operations. The simplest class of native operations are transversal gates, which are naturally fault-tolerant. Here, in this paper, we aim to characterize the transversal gates of quantum Reed–Muller (RM) codes by exploiting the well-studied properties of their classical counterparts. We start our work by establishing a new geometric characterization of quantum RM codes via the Boolean hypercube and its associated subcube complex. More specifically, a set of stabilizer generators for a quantum RM code can be described via transversal X and Z operators acting on subcubes of particular dimensions. This characterization leads us to define subcube operators composed of single-qubit π/2 k Z -rotations that act on subcubes of given dimensions. We first characterize the action of subcube operators on the code space: depending on the dimension of the subcube, these operators either (1) act as a logical identity on the code space, (2) implement non-trivial logic, or (3) rotate a state away from the code space. Second, and more remarkably, we uncover that the logic implemented by these operators corresponds to circuits of multi-controlled-Z gates that have an explicit and simple combinatorial description. Overall, this suite of results yields a comprehensive understanding of a class of natural transversal operators for quantum RM codes.
Reed–Muller (RM) codes↗
Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations
Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.
97 MATHEMATICS AND COMPUTING↗
Super-transient scaling in time-delay autonomous Boolean network motifs
Autonomous Boolean networks are commonly used to model the dynamics of gene regulatory networks and allow for the prediction of stable dynamical attractors. However, most models do not account for time delays along the network links and noise, which are crucial features of real biological systems. Concentrating on two paradigmatic motifs, the toggle switch and the repressilator, we develop an experimental testbed that explicitly includes both inter-node time delays and noise using digital logic elements on field-programmable gate arrays. We observe transients that last millions to billions of characteristic time scales and scale exponentially with the amount of time delays between nodes, a phenomenon known as super-transient scaling. We develop a hybrid model that includes time delays along network links and allows for stochastic variation in the delays. Using this model, we explain the observed super-transient scaling of both motifs and recreate the experimentally measured transient distributions.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Ferroelectric symmetry-protected multibit memory cell
Here, the tunability of electrical polarization in ferroelectrics is instrumental to their applications in information-storage devices. The existing ferroelectric memory cells are based on the two-level storage capacity with the standard binary logics. However, the latter have reached its fundamental limitations. Here we propose ferroelectric multibit cells (FMBC) utilizing the ability of multiaxial ferroelectric materials to pin the polarization at a sequence of the multistable states. Employing the catastrophe theory principles we show that these states are symmetry-protected against the information loss and thus realize novel topologically-controlled access memory (TAM). Our findings enable developing a platform for the emergent many-valued non-Boolean information technology and target challenges posed by needs of quantum and neuromorphic computing.
36 MATERIALS SCIENCE↗
Security analysis of boolean algebra based on Zhang-Wang digital signature scheme
In 2005, Zhang and Wang proposed an improvement signature scheme without using one-way hash function and message redundancy. In this paper, we show that this scheme exits potential safety concerns through the analysis of boolean algebra, such as bitwise exclusive-or, and point out that mapping is not one to one between assembly instructions and machine code actually by means of the analysis of the result of the assembly program segment, and which possibly causes safety problems unknown to the software.
97 MATHEMATICS AND COMPUTING↗