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Abstract This paper presents theoretical analysis and design procedures for low noise amplifiers (LNAs) in advanced CMOS technologies. For demonstration, a 30‐GHz LNA designed for 5G millimeter‐wave communication systems was fabricated in a 65‐nm CMOS process. It provides a power gain of 22.6 dB with a noise figure of 3.2 dB while drawing 7.3 mW from a 1.2 V supply.
As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.
Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.
The test results of measurements performed on two different sizes of ferroelectric random access memory (FeRAM) suggest the degradation is due to the low radiation tolerance of sense amplifiers and reference voltage generators which are based on commercial complementary metal oxide semiconductor (CMOS) technology. This paper presents total ionizing dose (TID) testing of 64Kb Ramtron FM1608 and 256Kb Ramtron FM1808.
Low-power, low-cost, miniature and integrated digital imaging systems are expected to be widely used in consumer electronics in the near future. While CMOS technology has been responsible for the phenomenal growth in consumer electronics, micro-porcessors, memory, audio systems, and radio-frequency circuits (e.g. cellular phones), till recently, the video technology remained outside this mainstream.
We have been developing a 32 x 32 prototype array of individually addressable Micro-Mirrors capable of operating at cryogenic temperature for Earth and Space Science applications. Micro-Mirror-Array technology has the potential to revolutionize imaging and spectroscopy systems for NASA's missions of the 21st century. They can be used as programmable slits for the Next Generation Space Telescope, as smart sensors for a steerable spectrometer, as neutral density filters for bright scene attenuation etc. The, entire fabrication process is carried out in the Detector Development Laboratory at NASA, GSFC. The fabrication process is low temperature compatible and involves integration of conventional CMOS technology and surface micro-machining used in MEMS. Aluminum is used as the mirror material and is built on a silicon substrate containing the CMOS address circuit. The mirrors are 100 microns x l00 microns in area and deflect by +/- 10 deg induced by electrostatic actuation between two parallel plate capacitors. A pair of thin aluminum torsion straps allow the mirrors to tilt. Finite-element-analysis and closed form solutions using electrostatic and mechanical torque for mirror operation were developed and the results were compared with laboratory performance. The results agree well both at room temperature and at cryogenic temperature. The development demonstrates the first cryogenic operation of two-dimensional Micro-Mirrors with bi-state operation. Larger arrays will be developed meeting requirements for different science applications. Theoretical analysis, fabrication process, laboratory test results and different science applications will be described in detail.
Topological semimetals contain novel combinations of properties that make them useful in a variety of applications, including optoelectronics, spintronics and low energy computing, and catalysis. Although they have been grown with high quality as bulk single crystals, incorporation with semiconductor substrates will ultimately be required to maximize their technological reach. Here, epitaxial growth of the Dirac semimetal Cd3As2 on Si(001) is demonstrated through two routes. First, Cd3As2(112) epilayers are grown on Si(001) via an intermediate CdTe(111) buffer layer. Second, Cd3As2(112) is grown directly on Si(001). This work sets the foundation for integration of novel semimetal materials with existing CMOS technology.
Resistive switching, a behavior found in many oxide materials, has the potential to enable emerging computer hardware technologies and architectures. We present resistive switching devices fabricated from epitaxial brownmillerite SrFeO2.5 films with two distinct film orientations, wherein facile oxygen ion diffusion planes are aligned parallel (in-plane) and perpendicular (out-of-plane) with the electrodes. SrFeO2.5 films were grown on (001) oriented Nb:SrTiO3 to enable high-quality interfaces and future integration with Si CMOS technologies. Post-growth vacuum annealing and growth pressure were used to control film orientations, as confirmed by transmission electron microscopy and x-ray diffraction measurements. Films grown with diffusion planes oriented in-plane had oxygen-rich, perovskite-like nanodomains spread throughout the film, and fabricated devices exhibited worse switching consistency and more stochasticity. In contrast, films grown with diffusion planes oriented out-of-plane had a more uniform oxygen-rich perovskite interfacial layer above the bottom electrode, and devices built from this film orientation showed significant statistical improvements in switching voltages and cycling consistency.
For more than three decades now, CMOS technology has been the backbone behind the phenomenal advances in low-cost, low-power, reliable, highly integrated and miniaturized system development.
Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.
An electronic timer has been developed for sounding rocket use. The timer uses CMOS technology for low power consumption and has a battery back-up to keep the timing circuit active in case of a dropout on the payload power bus. Time-event decoding is done by programming EPROM's which enable a +28 volt dc sourcing output. There are 32 discrete outputs which can provide +28 volt dc into a minimum load impedance of 150 ohms. Inputs are designed to operate on standard CMOS voltage levels, but they can withstand +28 volts dc without damage. The timer can be started by either 'G' or lift-off switch closure or umbilical release at lift-off.
Recent Findings from Audits, New Technology Data Reviews a) Disabled Chip Burn-ins A recent audit for a QML device discovered that the chip was disabled during the static burn-in, thus it was not drawing any current. Recommendation: For new SMDs add a statement within the burn-in paragraphs stating that the parts shall be kept in their enabled state during the burn-in. b) Class Q 160-hr/125oC Burn-in This is being interpreted as a static burn-in (even for CMOS technology). Recommendation: Provide clarification in MIL-STD-883, Test Method 5004. c) At Frequency (Dynamic) Burn-ins Test equipment limitation is being cited for not doing burn-ins at the application frequency. Recommendation: The burn-in task group to discuss and provide guidance. When the SMD says that the part can be used at 200 MHz, then doing burn-in at 6 MHz (cited as burn-in equipment limitation frequency) is not going to be meaningful! d) Two Static Burn-ins Some manufacturers are doing electrical testing between the two static burn-ins, whereas others do electricals after completing both static burn-ins. Recommendation: Provide clarification in MIL-STD-883, Test Method 5004. e) Thermal Imaging For a device with hot spots, the thermal resistance, junction-to-case, would be much higher than the guidelines given in MIL-STD-1835. One of the suppliers used thermal imaging to find hot spots on the die. Recommendation: Assign a task group to evaluate the effectiveness of thermal imaging at the product development stage.
Abstract Resistive switching devices herald a transformative technology for memory and computation, offering considerable advantages in performance and energy efficiency. Here, a simple and scalable material system of conductive oxide interfaces is employed, and their unique properties are leveraged for a new type of resistive switching device. An Al 2 O 3 –TiO 2 ‐based valence‐change resistive switching device, where the conductive oxide interface serves both as the bottom electrode and as a reservoir of defects for switching, is demonstrated. The amorphous–polycrystalline Al 2 O 3 –TiO 2 conductive interface is obtained following the technological path of simplifying the fabrication of the 2D electron gases (2DEGs), making them scalable for practical mass integration. Physical analysis of the device chemistry and microstructure with comprehensive electrical analysis of its switching behavior and performance is combined. The origin of the resistive switching is pinpointed to the conductive oxide interface, which serves both as the bottom electrode and as a reservoir of oxygen vacancies. The latter plays a key role in valence‐change resistive switching devices. The new device, based on scalable and complementary metal–oxide–semiconductor (CMOS)‐technology‐compatible fabrication processes, opens new design spaces toward increased tunability and simplification of the device selection challenge.
We have developed a concept design for a large (~10k x 10k) CMOS imaging array whose elements are grouped in small subarrays with N pixels in each. The subarrays are code-division multiplexed using the Hadamard Transform (HT) based encoding. The Hadamard code improves the signal-to-noise (SNR) ratio to the reference of the read-out amplifier by a factor of N^1/2. This way of grouping pixels reduces the number of hybridization bumps by N. A single chip layout has been designed and the architecture of the imager has been developed to accommodate the HT base multiplexing into the existing CMOS technology. The imager architecture allows for a trade-off between the speed and the sensitivity. The envisioned imager would operate at a speed >100 fps with the pixel noise < 20 e-. The power dissipation would be ~100 pW/pixe1. The combination of the large format, high speed, high sensitivity and low power dissipation can be very attractive for space reconnaissance applications.
This article deals with research, development and future directions of magnetoelectric composites for practical devices applications. In the past 20 years there has been a surge of research in the area of multiferroics (MF) and magnetoelectrics (ME) due to their potential to replace existing technologies based only on ferroelectric or ferromagnetic materials. Some of the magnetoelectric composites show exceptionally high potential in the area of magnetic field sensors, however, work remains before commercialization can be realized. The cross coupling among various ferroic parameters in magnetoelectric composites is several orders higher than single phase magetoelectrics, which make its favorable for low detection (nT or pT) magnetic field sensors. Advances in both layered structures or controlled three-dimensional matrix composites for applications as magnetoelectric nonvolatile memory elements are both required. Robust cross-coupling among various parameters with more than four logic states and its compatibility with complementary-symmetry metal–oxide–semiconductor (CMOS) technology are the main requirements for heterostructure magnetoelectric thin films. The major hurdles in the area of magnetoelectric nonvolatile memory elements are poor interfacial properties and weak magnetoelectric coupling for high density fast read and write processes. Another potential area is strained coupled magneto-electric composites where magnetostriction mediated dimensional change in the magnetic layer effectively modulate the change in the dimension of piezoelectric layers via piezostriction, which leads to a strong ME coupling where their coupling magnitude is sufficient for magnetic field sensors. Energy harvesters based on magnetoelectric composites are also intriguing concepts to capture various types of waste energy, in the form mechanical vibration, pressure, wind energy, hydrothermal and waste temperature.
The complexity of information processing in the brain requires the development of technologies that can provide spatial and temporal resolution by means of dense electrode arrays paired with high-channel-count signal acquisition electronics. In this work, we present an ultra-low noise modular 512-channel neural recording circuit that is scalable to up to 4096 simultaneously recording channels. The neural readout application-specific integrated circuit (ASIC) uses a dense 8.2 mm × 6.8 mm 2D layout to enable high-channel count, creating an ultra-light 350 mg flexible module. The module can be deployed on headstages for small animals like rodents and songbirds, and it can be integrated with a variety of electrode arrays. The chip was fabricated in a TSMC 0.18 µm 1.8 V CMOS technology and dissipates a total of 125 mW. Each DC-coupled channel features a gain and bandwidth programmable analog front-end along with 14 b analog-to-digital conversion at speeds up to 30 kS/s. Additionally, each front-end includes programmable electrode plating and electrode impedance measurement capability. We present both standalone and in vivo measurements results, demonstrating the readout of spikes and field potentials that are modulated by a sensory input.
While the complementary metal-oxide semiconductor (CMOS) technology is the mainstream for the hardware implementation of neural networks, an alternative route is explored based on a new class of spiking oscillators called “thermal neuristors”, which operate and interact solely via thermal processes. Utilizing the insulator-to-metal transition (IMT) in vanadium dioxide, a wide variety of reconfigurable electrical dynamics mirroring biological neurons is demonstrated. Notably, inhibitory functionality is achieved just in a single oxide device, and cascaded information flow is realized exclusively through thermal interactions. To elucidate the underlying mechanisms of the neuristors, a detailed theoretical model is developed, which accurately reflects the experimental results. In conclusion, this study establishes the foundation for scalable and energy-efficient thermal neural networks, fostering progress in brain-inspired computing.
2D van der Waals (vdW) magnets open landmark horizons in the development of innovative spintronic device architectures. However, their fabrication with large scale poses challenges due to high synthesis temperatures (>500 °C) and difficulties in integrating them with standard complementary metal-oxide semiconductor (CMOS) technology on amorphous substrates such as silicon oxide (SiO 2 ) and silicon nitride (SiN x ). Here, a seeded growth technique for crystallizing CrTe 2 films on amorphous SiN x /Si and SiO 2 /Si substrates with a low thermal budget is presented. This fabrication process optimizes large-scale, granular atomic layers on amorphous substrates, yielding a substantial coercivity of 11.5 kilo-oersted, attributed to weak intergranular exchange coupling. Field-driven Néel-type stripe domain dynamics explain the amplified coercivity. Moreover, the granular CrTe 2 devices on Si wafers display significantly enhanced magnetoresistance, more than doubling that of single-crystalline counterparts. Current-assisted magnetization switching, enabled by a substantial spin–orbit torque with a large spin Hall angle (85) and spin Hall conductivity (1.02 × 10 7 ℏ/2e Ω -1 m -1 ), is also demonstrated. These observations underscore the proficiency in manipulating crystallinity within integrated 2D magnetic films on Si wafers, paving the way for large-scale batch manufacturing of practical magnetoelectronic and spintronic devices, heralding a new era of technological innovation.