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At least 55 records · Page 3

Harnessing ferro-valleytricity in pentalayer rhombohedral graphene for memory and compute

Two-dimensional materials with multiple degrees of freedom, including spin, valleys, and orbitals, open up an exciting avenue for engineering multifunctional devices. Beyond spintronics, these degrees of freedom can lead to novel quantum effects such as valley-dependent Hall effects and orbital magnetism, which could revolutionize next-generation electronics. However, achieving independent control over valley polarization and orbital magnetism has been a challenge due to the need for large electric fields. A recent breakthrough involving pentalayer rhombohedral graphene has demonstrated the ability to individually manipulate anomalous Hall signals and orbital magnetic hysteresis, forming what is known as a valley-magnetic quartet. Here, we leverage the electrically tunable ferro-valleytricity of pentalayer rhombohedral graphene to develop nonvolatile memory and in-memory computation applications. We propose an architecture for a dense, scalable, and selector-less nonvolatile memory array that harnesses the electrically tunable ferro-valleytricity. In our designed array architecture, nondestructive read and write operations are conducted by sensing the valley state through two different pairs of terminals, allowing for independent optimization of read/write peripheral circuits. The power consumption of our PRG-based array is remarkably low, with only ∼6 nW required per write operation and ∼2.3 nW per read operation per cell. This consumption is orders of magnitude lower than that of the majority of state-of-the-art cryogenic memories. Additionally, we engineer in-memory computation by implementing majority logic operations within our proposed nonvolatile memory array without modifying the peripheral circuitry. In conclusion, our framework presents a promising pathway toward achieving ultra-dense cryogenic memory and in-memory computation capabilities.

2D materials↗

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

97 MATHEMATICS AND COMPUTING↗

Low‐Volume Cores for Fabrication of Compact, Versatile, and Intelligent Soft Systems

Abstract This study introduces the low‐volume core (LVC) fabrication method, which enables the monolithic molding of compact, complex, versatile, and intelligent soft robotic systems. This method uses thin and flexible thermoplastic sheets to mold internal chambers in soft fluidic actuators, valves, and circuits. The LVC fabrication method creates low‐volume networks in soft actuators (LV‐net actuators) that can be made with compact and complex geometries, enabling both low actuation volume input and multi‐degree‐of‐freedom actuators. LVC fabrication can also be used for compact, completely soft, and monolithic logic components (valves with low‐volume core, also called as LV valves) to provide directional resistance as well as a switching mechanism that enables fluidic logic in soft systems. The compatibility of the fabrication methods for both soft actuators and valves facilitates the creation of compact, integrated, and versatile soft robotic systems with embodied intelligence. This study introduces two examples of such intelligent soft robotic systems that integrate both LV‐net actuators and LV valves to demonstrate capability for complex system fabrication.

Yu, Qifan↗

Noise-Directed Adaptive Remapping for Integer Optimization: from qubits to (encoded) qudits

We extend Noise-Directed Adaptive Remapping (NDAR), a recently proposed heuristic meta-algorithm that leverages device noise as a computational resource, to optimization problems over discrete (integer) domains. While originally introduced for unconstrained binary optimization, the proposed generalization introduces additional gauge degrees of freedom at the logical level, such that the gauge transformation applied at each iteration is no longer unique, allowing tailoring to particular encodings or quantum hardware. We identify encoding-dependent requirements for NDAR beyond binary domains: feasibility of the noise attractor, existence of compatible gauge transformations that preserve an efficiently implementable circuit family, and a systematic way to select the transform to apply at each step. We analyze these criteria for qudit-native and for binary, one-hot, and domain-wall qubit encodings, using the Max-k-colorable subgraph problem as a running example. We demonstrate that these encodings can exhibit distinct advantages and tradeoffs when integrated within the NDAR framework, particularly in how noise-induced dynamics interact with the solution landscape and choice of encoding. Our results indicate that NDAR-guided noise considerations provide a new criterion for comparing device-level encoding choices for quantum optimization. Finally, we outline directions toward experimental realization in superconducting qudit devices and further algorithmic improvements.

Hadfield, Stuart [RIACS, Mtn. View] (ORCID:0000000↗

Surface-Functionalized, Two-Dimensional Polymer Electrochromic Layers as Ultrafast, Multi-State Infrared Optical Gates

Electrochromic devices have widespread application potential, but the currently available switching speeds limit broad real-world implementation of this technology. Here, we report surface-engineered two-dimensional polymers with ionophilic pores that offer unprecedented switching speeds in solid-state, two-terminal, electrochromic devices. In particular, we demonstrate that a crystalline donor–acceptor 2DP functionalized with ethylene glycol oligomers exhibits multistate infrared absorption that is 4× faster (t c = 320 ms) with 3× coloration efficiency (491 cm 2 C –1 ) compared to an alkyl functionalized 2DP constructed from the same chromophores. The functionalized nanoporous surfaces enable rapid switching in these materials under either oxidative or reductive conditions, allowing us to access a range of robust, stable optical responses in a single electrochromic layer. These attributes led us to leverage surface-functionalized 2DPs as multistate infrared logic gates. Collectively, this work demonstrates that surface engineering of nanoporous crystalline lattices is a promising approach to co-optimize the electronic and ionic conductivities required to achieve rapidly switchable electrochromic layers. Beyond speed and efficiency, the demonstration of multistate infrared characteristics shows that electrochromic frameworks are useful in integrated optoelectronic circuits. This positions surface-engineered 2DPs as improved electrochromic coatings and a new material platform for photonic information processing and adaptive devices.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Quantum Sensing using Geometrical Phase in Qubit-Oscillator Systems

We present a quantum sensing protocol for coupled qubit-oscillator systems that surpasses the standard quantum limit (SQL) by exploiting a geometrical phase. The signal is encoded in the geometrical phase that is proportional to the area enclosed in oscillator phase space. This area is amplified through squeezing, enabling sensitivities beyond the SQL. Our method is independent of oscillator's initial state, amenable to sensing with high-temperature or logical error-corrected states. The protocol shows robustness to qubit Markovian noise and preserves its state-independence, underscoring its practicality for next-generation quantum metrology. We demonstrate application to force sensing beyond the SQL in longitudinally coupled systems, and to high-precision measurements of couplings and pulse calibration surpassing SQL in dispersively coupled circuit quantum electrodynamics (cQED) architectures.

Suri, Nishchay [LBNL, Berkeley]↗

Quantum Fourier Transform with Leakage Control

In circuit QED (cQED) systems, one can manipulate the cavity Fock states to use quantum processing unit (QPU). Since the coherence times of the Fock states are long, qudit based computation can be possible. One of the most basic gate that can be engineered in this cQED platform is the displacement gate, $D(\alpha)$. However, accessible number of qudit-levels is finite. The truncated displacement gate on the qudit is the source of theoretical error above the logical states and needs to be addressed. In this work, we monitor and minimize the leakage in qudit systems that involves displacement gate by introducing so-called `bumper' states and a modified cost function.

Kurkcuoglu, D. [Fermilab] (ORCID:0000000311097074)↗

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study of these two architectures under both dimensional scaling ( XY/Z shrinkage) and vertical integration (increasing stacked capacitors per cell). Using technology computer-aided design (TCAD) and circuit-level simulations, we analyze how scaling impacts ferroelectric capacitance, parasitic coupling, and floating-node (FN) dynamics, which together dictate sense margin (SM) and read stability. A key mitigation strategy—floating unselected capacitors—is applied to both architectures, effectively decoupling the SM from the number of stacked capacitors and enabling tractable analysis across scaling regimes. Results show that 1T-nC suffers more from charge sharing with the bitline (BL), while 2T-nC benefits from transistor isolation and stronger low-voltage sensing at the cost of increased area. By systematically evaluating these behaviors across scaling directions, this work establishes the reliability trade-offs of 1T-nC and 2T-nC cells and provides design guidelines for high-density, vertically integrated FeRAM systems.

1T-nC↗

Petahertz electronics

Petahertz, or lightwave, electronics uses tailored optical waveforms to control charge carriers in an electronic circuit at petahertz frequencies. This may enable faster processing than conventional pulsed electronics, which cannot be scaled beyond gigahertz frequencies. In recent years, petahertz-scale currents driven by optical fields have been measured in solid-state systems and nanoscale structures, with several proof-of-principle demonstrations of sub-optical-cycle current generation and optical-field-resolved waveform detection at the sub-femtosecond to few-femtosecond scale. Recent work has taken the first steps towards digital and quantum operation by exploring optical-field-driven logic and memory functionality. Here, in this Review, we discuss the progress towards sub-cycle field-driven current injection, highlighting key theoretical concepts, experimental milestones, and questions remaining as we push towards realizing petahertz electronics for ultrafast optical waveform analysis, digital logic, communications, and quantum computation.

Heide, Christian↗

A Generic and Multifunctional Electromagnetic Transient Model for Grid-Following Inverters

This article presents a generic and multi-functional electromagnetic transient (EMT) dynamic model of grid following (GFL) inverter-based resource (IBR) using the PSCAD software platform. The features of the developed model includes the flexibility in selecting various types and combinations of DC sources covering PV modules, battery modules, ideal DC source module, as well as flexibility in selecting either switched or averaged model of inverter. This model also covers exhaustive lists of controller logic covering open-loop/closed-loop PQ dispatch control, DC voltage and AC terminal voltage control along with the conventional current control designed in dq-domain, ate- domain and positive-negative sequence domain. Moreover, this model is equipped with the flexibility in selecting various types of current limiting schemes that includes saturation-based as well as latching-based current limiter, anti-windup protection. Moreover, the EMT model is agnostic to the MVA rating and is suitable for interfacing transmission systems by being complaint with the IEEE Std. 2800. The generality in the power circuits and the multi-functional options in operation and control of the developed EMT model makes it suitable for both academia and industry to study various power system aspects not limited to but such as fault behavior of GFL IBR and impacts on protection system, transient stability of a system interfaced with large number of GFL IBRs etc.

14 SOLAR ENERGY↗

A Generic and Multi-Functional Electromagnetic Transient Model for Grid-Following Inverter: Preprint

This article presents a generic and multi-functional electromagnetic transient (EMT) dynamic model of grid following (GFL) inverter-based resource (IBR) using the PSCAD TM software platform. The features of the developed model includes the flexibility in selecting various types and combinations of DC sources covering PV modules, battery modules, ideal DC source module, as well as flexibility in selecting either switched or averaged model of inverter. This model also covers exhaustive lists of controller logic covering open-loop/closed-loop PQ dispatch control, DC voltage and AC terminal voltage control along with the conventional current control designed in dq-domain, aB- domain and positive-negative sequence domain. Moreover, this model is equipped with the flexibility in selecting various types of current limiting schemes that includes saturation-based as well as latching-based current limiter, anti-windup protection. Moreover, the EMT model is agnostic to the MVA rating and is suitable for interfacing transmission systems by being complaint with the IEEE Std. 2800. The generality in the power circuits and the multi-functional options in operation and control of the developed EMT model makes it suitable for both academia and industry to study various power system aspects not limited to but such as fault behavior of GFL IBR and impacts on protection system, transient stability of a system interfaced with large number of GFL IBRs etc.

grid following inverter↗

Quantum Zeno Monte Carlo for computing observables

The recent development of logical quantum processors marks a pivotal transition from the noisy intermediate-scale quantum (NISQ) era to the fault-tolerant quantum computing (FTQC) era. These devices have the potential to address classically challenging problems with polynomial computational time using quantum properties. However, they remain susceptible to noise, necessitating noise resilient algorithms. We introduce Quantum Zeno Monte Carlo (QZMC), a classical-quantum hybrid algorithm that demonstrates resilience to device noise and Trotter errors while showing polynomial computational cost for a gapped system. QZMC computes static and dynamic properties without requiring initial state overlap or variational parameters, offering reduced quantum circuit depth.

Han, Mancheon [Korea Institute for Advanced Study ↗

ML–Enabled FPGA Framework for Fast Quantum State Discrimination in Mid-Circuit Measurement Regimes

Accurate and low-latency quantum state discrimination is essential for protocols involving mid-circuit measurement (MCM) and conditional feed-forward. In superconducting quantum systems, conventional readout pipelines transfer measurement data to host processors for post-processing, introducing millisecond-scale delays that far exceed qubit coherence times. To overcome this bottleneck, we present an in-situ machine learning (ML) inference engine implemented on an FPGA for real-time quantum state discrimination. Our design performs inference directly on digitized readout signals with 40 ns latency, supports both qubit and qutrit readout, and enables conditional operations without host-side intervention. This capability is critical for MCM and for feedback-driven protocols such as quantum error correction. We validate the system on superconducting transmon hardware, demonstrating robust discrimination fidelity across multiple qubit and qutrit channels. We further demonstrate conditional qutrit logic driven by FPGA-resident classification, highlighting the potential of low-latency ML-on-FPGA control for NISQ applications and scalable fault-tolerant quantum computing.

Vora, Neel [Lawrence Berkeley National Laboratory ↗

A scalable superconducting nanowire memory array with row–column addressing

Scalable superconducting memory is required for the development of low-energy superconducting computers and fault-tolerant quantum computers. Conventional superconducting logic-based memory cells possess a large footprint that limits scaling; nanowire-based superconducting memory cells, although more compact, have high error rates, which hinders integration into large arrays. Here we report a 4 × 4 superconducting nanowire memory array that is designed for scalable row–column operations and has a functional density of 2.6 Mbit cm −2 . Each memory cell is based on a nanowire loop consisting of two temperature-dependent superconducting switches and a variable kinetic inductor. The arrays operate at 1.3 K, where we implement and characterize multiflux quanta state storage and destructive read-out. By optimizing the write- and read-pulse sequences, we minimize bit errors and maximize operating margins. We achieve a minimum bit error rate of 10 −5 . Here, we also use circuit-level simulations to understand the memory cell’s dynamics, performance limits and stability under varying pulse amplitudes.

Electrical and electronic engineering↗

A Survey on the Expanding Scope and Interdisciplinary Opportunities for Processing-in-Memory Techniques

Processing-in-Memory (PIM) is emerging as a practical path to overcome the limitations of traditional von Neumann architectures. At its core, PIM systems implement computing primitives such as logic operations and multiply-accumulate acceleration through compute-in-memory, near-memory processing, or hybrid designs. The role of memory cells varies widely across technologies, acting as inputs, outputs, or analog accumulators through bit-lines and sense amplifiers. This diversity creates trade-offs in precision, bandwidth, latency, and programmability, making it difficult to build a unified understanding on the progress of the field. In this survey, we organize recent advances of PIM into three areas. First, we discuss the progress on the architectural optimizations of PIM and its integration with both DRAM and emerging non-volatile memories. Second, we examine how PIM is being used to accelerate key computing domains, including generative AI workloads and high-performance kernels, along with new approaches. Third, we highlight the growing adoption of PIM in computational sciences, where it is being applied to solve interdisciplinary problems such as genome analysis, mRNA quantification, mass spectrometry, quantum circuit simulation, wave modeling, and secure computation. Finally, we synthesize the major challenges that continue to slow PIM adoption, including manufacturing constraints, power delivery, thermal reliability, data consistency, runtime and memory-management coordination, and the difficulty of building portable software abstractions without sacrificing commercial viability. This work provides an updated, structured perspective on PIM’s potential across computing and computational sciences and the barriers that must be solved for it to reach its full impact.

Asifuzzaman, Kazi [Oak Ridge National Laboratory (↗

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗

Direct pulse-level compilation of arbitrary quantum logic gates on superconducting qutrits

Advanced simulations and calculations on quantum computers require high-fidelity implementations of quantum operations. The universal gateset approach builds complex unitaries from a small set of primitive gates, often resulting in a long gate sequence, which is typically a leading factor in the total accumulated error. Compiling a complex unitary for processors with higher-dimensional logical elements, such as qutrits, exacerbates the accumulated error per unitary, since an even longer gate sequence is required. Optimal control methods promise time- and resource-efficient compact gate sequences and, therefore, higher fidelity. These methods generate pulses that can directly implement any complex unitary on a quantum device. In this work, we demonstrate that any arbitrary qubit and qutrit gate can be realized with high fidelity, which can significantly reduce the length of a gate sequence. We generate and test pulses for a large set of randomly selected arbitrary unitaries on several quantum processing units (QPUs): the Lawrence Livermore National Laboratory Quantum Device and Integration Testbed’s (QuDIT’s) standard QPU and three of Rigetti’s QPUs: Ankaa-2, Ankaa-9Q-1, and Aspen-M-3. On the QuDIT platform’s standard QPU, the average fidelity of random qutrit gates is 97.9 ± 0.5% measured with conventional QPT and 98.8 ± 0.6% from QPT with gate folding. Rigetti’s Ankaa-2 achieves random qubit gates with an average fidelity of 98.4 ± 0.5% (conventional QPT) and 99.7 ± 0.1% (QPT with gate folding). On Ankaa-9Q-1 and Aspen-M-3, the average fidelities with conventional qubit QPT measurements were higher than 99% (see Appendix). Here we show that optimal control gates are robust to drift for at least 3 h and that the same calibration parameters can be used for all implemented gates. Our work promises that the calibration overheads for optimal control gates can be made small enough to enable efficient quantum circuits based on this technique.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗