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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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49 records · Page 3

Monolithic transistor gate energy recovery system

Energy is recovered from an insulated gate semiconductor switch, such as a MOSFET, that is otherwise lost in the gate capacitance by producing a notch in the gate control voltage for an interval B following an interval A after initial application of a gate control voltage pulse for turning the switch on, and a notch for an interval C following termination of the gate control voltage pulse followed by interval D during which the switch is turned on again, where each interval is a period .DELTA.T given by ##EQU1## L.sub.s is the inductance (discrete and/or parasitic) in series with the gate electrode of the insulated gate semiconductor switch, and C.sub.in is the capacitance of that switch between its gate and source electrodes. The interval .DELTA.T may be provided directly by timing in a pulse forming circuit for the gate control voltage applied, or adaptively by sensing the gate voltage v.sub.g and comparing it with fixed progressively higher voltages v.sub.1, v.sub.2 and v.sub.3, where v.sub.2 is intermediate v.sub.1 and v.sub.3 which correspond to the lower and upper levels of v.sub.g as the switch is turned off and on.

Rippel, Wally E.↗

Conversion Losses In GaAs Schottky-Barrier Diodes

Parasitic losses reduced with lightly doped epitaxial layers of proper thickness. Report presents calculations of conversion losses in Schottky-barrier diodes. Theoretical work directed toward reduction of parasitic losses through proper design of space-charge layers; possible, to reduce barrier capacitances and contributions to barrier resistances from undepleted epitaxial layers.

Von Roos, Oldwig↗

Conversion losses in GaAs Schottky-barrier diodes

The conversion losses of a Schottky-barrier diode have been calculated for a set of realistic diode parameters. It is found that previous work overestimated the substrate losses by 30 percent. It is also shown that a lightly doped epitaxial layer will decrease the barrier capacitance and with properly designed thickness will avoid any resistance losses due to this layer. Parasitic losses can thus be reduced substantially.

Von Roos, O.↗

Electrochemical Ultracapacitors Using Graphitic Nanostacks

Electrochemical ultracapacitors (ECs) have been developed using graphitic nanostacks as the electrode material. The advantages of this technology will be the reduction of device size due to superior power densities and relative powers compared to traditional activated carbon electrodes. External testing showed that these materials display reduced discharge response times compared to state-of-the-art materials. Such applications are advantageous for pulsed power applications such as burst communications (satellites, cell phones), electromechanical actuators, and battery load leveling in electric vehicles. These carbon nanostructures are highly conductive and offer an ordered mesopore network. These attributes will provide more complete electrolyte wetting, and faster release of stored charge compared to activated carbon. Electrochemical capacitor (EC) electrode materials were developed using commercially available nanomaterials and modifying them to exploit their energy storage properties. These materials would be an improvement over current ECs that employ activated carbon as the electrode material. Commercially available graphite nanofibers (GNFs) are used as precursor materials for the synthesis of graphitic nanostacks (GNSs). These materials offer much greater surface area than graphite flakes. Additionally, these materials offer a superior electrical conductivity and a greater average pore size compared to activated carbon electrodes. The state of the art in EC development uses activated carbon (AC) as the electrode material. AC has a high surface area, but its small average pore size inhibits electrolyte ingress/egress. Additionally, AC has a higher resistivity, which generates parasitic heating in high-power applications. This work focuses on fabricating EC from carbon that has a very different structure by increasing the surface area of the GNF by intercalation or exfoliation of the graphitic basal planes. Additionally, various functionalities to the GNS surface will be added that can exhibit pseudocapacitance. This pseudocapacitance exhibits faradaic (charge transfer) properties that can further increase the overall relative and volumetric capacitance of the material. A process is also proposed to use GNF as a precursor material to fabricate GNS that will be used as EC electrodes. This results in much better electrical conductivity than activated carbon. This is advantageous for high-pulsed-power applications to reduce parasitic heating. Larger average pore size allows more complete electrolyte wetting (faster charge transfer kinetics). These properties contribute to a lowered equivalent series resistance (ESR), increased specific power, shorter charging times, and decreased parasitic heating. The high density of basal plane edges provides nucleation sites for activation (addition of hydrophilic functional groups) that facilitate electrolyte wetting, and will contribute to pseudocapacitance.

Marotta, Christopher↗

Impedance Matching a Quarter Wave Resonant Receiver to Improve Efficiency in Unipolar Capacitive Wireless Power Transfer

Impedance matching techniques to achieve high performance in conventional wireless power transfer (WPT) systems are well established. These WPT systems are modelled as a lumped circuit, where the voltages/currents are approximately uniform and mostly unaffected by parasitic elements. However, a group of WPT techniques exist that utilize parasitic elements to form a highly resonant power transfer condition at high quality factors, exploiting a distributed circuit operation that can be modeled as a mutually coupled transmission line. A calculated matching network typically becomes unmatched when connected to the transmission line, as it changes the electrical structure of the coupled transmission line. This is particularly true for WPT systems that use quarter wave (QWR) or half wave resonators (HWR) for the receiver. Here we present one technique of matching to a mutually coupled transmission line where a parallel path is formed that improves the power transfer efficiency without severely altering the transmission line characteristics.

Wireless↗

Parasitic suppressing circuit

A circuit for suppressing parasitic oscillations across an inductor operating in a resonant mode is described. The circuit includes a switch means and resistive means connected serially across the inductor. A unidirectional resistive-capacitive network is also connected across the inductor and to the switch means to automatically render the switch means conducting when inductive current through the inductor ceases to flow.

Fowler, J. T.↗

The Space Station Photovoltaic Panels Plasma Interaction Test Program: Test plan and results

The Plasma Interaction Test performed on two space station solar array panels is addressed. This includes a discussion of the test requirements, test plan, experimental set-up, and test results. It was found that parasitic current collection was insignificant (0.3 percent of the solar array delivered power). The measured arcing threshold ranged from -210 to -457 V with respect to the plasma potential. Furthermore, the dynamic response of the panels showed the panel time constant to range between 1 and 5 microsec, and the panel capacitance to be between .01 and .02 microF.

Nahra, Henry K.↗

The Space Station photovoltaic panels plasma interaction test program - Test plan and results

The plasma Interaction Test performed on two space station solar array panels is addressed. This includes a discussion of the test requirements, test plan, experimental set-up, and test results. It was found that parasitic current collection was insignificant (0.3 percent of the solar array delivered power). The measured arcing threshold ranged from -210 to -457 V with respect to the plasma potential. Furthermore, the dynamic response of the panels showed the panel time constant to range between 1 and 5 microsec, and the panel capacitance to be between .01 and .02 microF.

Nahra, Henry K.↗

Design, fabrication, and performance of a whiskerless Schottky diode for millimeter and submillimeter wave applications

Design considerations, fabrication techniques, and performance predictions are presented for a planar whiskerless Schottky diode to be used (in radio astronomy applications) at 100-300 GHz. The anode and ohmic contacts are on the same side of the device, and proton bombardment is used to establish the divided surface (by making some regions of the GaAs wafer semiinsulating) prior to definition of a B-doped SiO2 finger, ohmic contacting, anode formation, and anode contact metallization (all using photolithographic techniques). The contributions of parasitic elements are calculated for a device with a 3.5-micron-deep n(+) layer doped at 2 x 10 to the 18th/cu cm, a 250-nm-thick epitaxial layer doped at 5 x 10 to the 16th/cu cm, and a 1-micron-radius anode (providing zero-bias junction capacitance 7 fE). It is predicted that such a device would have total series resistance 12.58 ohm and total shunt capacitance 1.37 fF, compared with 14.27 ohm and 0.93 fF for the corresponding whiskered device.

Mckinney, K.↗

Improved Capacitive Liquid Sensor

Improved capacitive sensor used to detect presence and/or measure thickness of layer of liquid. Electrical impedance or admittance of sensor measured at prescribed frequency, and thickness of liquid inferred from predetermined theoretical or experimental relationship between impedance and thickness. Sensor is basically a three-terminal device. Features interdigitated driving and sensing electrodes and peripheral coplanar ground electrode that reduces parasitic effects. Patent-pending because first to utilize ground plane as "shunting" electrode. System less expensive than infrared, microwave, or refractive-index systems. Sensor successfully evaluated in commercial production plants to characterize emulsions, slurries, and solutions.

Waldman, Francis A.↗

A Simple Control to Reduce the Voltage Stress of Non-Conducting Switches in Three-Level ANPC Converter

With the development of wide band-gap (WBG) technology, the switching speed of power semiconductor devices is increased, which makes circuits more sensitive to parasitics. For three-level active neutral point clamped (3L-ANPC) converters, the over-voltage of non-conducting switches can be an issue. This paper analyzes the multiple commutation loops in 3L-ANPC converter and summarizes the impact factors of the over-voltage for the non-conducting switch. It is found that the nonlinearity of the output capacitance of the device can significantly influence the over-voltage. A simple control without introducing any additional hardware circuit is proposed to attenuate the impact of the nonlinearity. With the proposed control, the peak over-voltage of the non-conducting switch can be reduced significantly. Multi-pulse test is conducted for a 3L- ANPC converter built with silicon carbide (SiC) MOSFETs. The testing results show that the peak over-voltage decreases from 892 V to 624 V with the proposed control. More detailed analysis and experimental results will be provided in the final paper.

SiC MOSFET↗

Miniaturized Wilkinson Power Dividers Utilizing Capacitive Loading

This letter reports the miniaturization of a planar Wilkinson power divider by capacitive loading of the quarter wave transmission lines employed in conventional Wilkinson power dividers. Reduction of the transmission line segments from lambda/4 to between lambda/5 and lambda/12 are reported here. The input and output lines at the three ports and the lines comprising the divider itself are coplanar waveguide (CPW) and asymmetric coplanar stripline (ACPS), respectively. The 10 GHZ power dividers are fabricated on high resistivity silicon (HRS) and alumina wafers. These miniaturized dividers are 74% smaller than conventional Wilkinson power dividers, and have a return loss better than +30 dB and an insertion loss less than 0.55 dB. Design equations and a discussion about the effect of parasitic reactance on the isolation are presented for the first time.

Scardelletti, Maximilian C.↗

Design, Fabrication and Evaluation of Deep Submicron FETs

GaAs FET's with gatelengths on a nanometer scale have been designed, fabricated and evaluated in order to investigate the limits of conventional GaAs scaling rules. An optimum layer structure for deep submicron GaAs MESFET's was designed, and a fabrication process that minimizes the effects of extrinsic parasitics was developed. The fabricated FET's were measured and evaluated at DC and at RF frequencies. 0.1 micron and 50 nm gatelength GaAs MESFET's with 2x45 micron wide "T"-shaped gates were fabricated so that a wide range of saturation current was achieved. For the 0.1 micron gatelength FET's, peak g(sub m,ext) varies from 611 mS/mm to 795 mS/mm with an average value of 717 mS/mm, peak f(sub t) varies from 90 GHz to 103 GHz with an average value of 96 GHz, and peak f(sub max) varies from 147 GHz to 172 GHz with an average value of 161 GHz. In comparison, the peak g(sub m,ext) of the 50 nm gatelength FET's is reduced by almost 20%, the peak f(sub t) is increased by 30%, and the peak f(sub max) is about the same as for the 0.1 micron gatelength FET's. The f(sub t) of the 50 nm gatelength FET's is higher than the f(sub t) of the 0.1 micron gatelength FET's because of the reduced gate-source capacitance (C(sub gs)). The peak f(sub max) does not show a similar improvement because of the onset of short channel effects.

Abbott-Morse, Tracy↗