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This irradiation campaign was performed to evaluate the destructive single event effect (SEE) susceptibility of a n-channel power MOSFET from SSDI for space-based instrumentation. Testing was performed at Michigan State University’s (MSU) Facility for Rate Isotope Beams (FRIB) using an LET of 50.5 MeV·cm 2 /mg
A simple passive circuit that improves current balance in parallelled power MOSFETs that are not precisely matched and that are operated in their active region from a common gate drive are exhibited. A nonlinear circuit consisting of diodes and resistors generates the differential gate potential required to correct for unbalance while maintaining low losses over a range of current. Also application of a thin tape wound magnetic core to effect dynamic current balance is reviewed, and a simple theory is presented showing that for operation in the active region the branch currents tend to revert to their normal unbalanced values even if the core is not driven into saturation. Results of several comparative experiments are given.
The purpose of this document is two-fold. First, the document lists and discusses many of the issues important to understand when testing power MOSFETs. Second, the recommended approach for using radiation test data to define the device application requirements is presented. These include SEE rate calculation, data analysis, and derating guidelines. A significant amount of work has been done on the basic effects of SEB and SEGR. References are supplied where seminal work has been done on the topic at hand. The reader is urged to review the references if the testing issues or mission application at hand are complex.
The relative importance of heavy-ion interaction with the oxide, charge ionized in the epilayer, and charge ionized in the drain substrate, on the bias for SEGR failure in vertical power MOSFETs is experimentally investigated. The results indicate that both the charge ionized in the epilayer and the ion atomic number are important parameters of SEGR failure. Implications on SEGR hardness assurance are discussed.
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A Technology Computer Aided Design (TCAD) simulation-based method is developed to evaluate whether derating of high-energy heavy-ion accelerator test data bounds the risk for single-event gate rupture (SEGR) from much higher energy on-orbit ions for a mission linear energy transfer (LET) requirement. It is shown that a typical derating factor of 0.75 applied to a single-event effect (SEE) response curve defined by high-energy accelerator SEGR test data provides reasonable on-orbit hardness assurance, although in a high-voltage power MOSFET, it did not bound the risk of failure.
High-performance power metal/oxide/semiconductor field-effect transistors (MOSFETs) fabricated in silicon carbide. Devices offer potential advantages over silicon-based MOSFETs, including lower "on" - state resistances at same rated voltages, ability to operate at higher temperatures, and higher thermal conductivity. Also more resistant to damage by ionizing radiation, an advantage for switching appications in nuclear facilities.
Variability of the solar energetic particle environment is investigated for single-event-burnout reliability of silicon-carbide power metal-oxide-semiconductor field effect transistors. A probabilistic assessment of failure evaluates the benefits of de-rating voltage, shielding, and mission length. The Prediction of Solar particle Yields for Characterizing Integrating Circuits code is used to calculate a cumulative density function for the fluence of the environment. The lethal ion method is then used to determine what proportion of the environment will cause single-event-burnout. The operating voltage determines the lowest linear-energy-transfer particle that will cause single-event-burnout and that should be included in the environment distribution. The shielding and mission length also determine the final environment distribution of the mission fluence. Through calculating the reliability for different operating voltages, shielding, and mission length for a specific device, it is shown that shielding thickness and operating voltage have a large effect on reliability and can be traded off during the design.
High efficiency, high density and galvanically isolated power converters are attractive for numerous medium voltage high power applications. This paper presents a 1.5kVdc, 100kW bidirectional Dual Active Half Bridge (DAHB) using newly developed 1.7kV SiC MOSFET modules. The DAHB achieved an efficiency of 98.6% at full load of 100kW and a maximum of 99% at 45kW, operating as an isolated DC/DC converter. The converter also achieved an efficiency of 97.8% operating as an isolated DC/AC inverter. An optimized PCB-based busbar design has significantly reduced the voltage overshoot across the device, making the design suitable for 1500Vdc input application such as 1500V PV inverters. Typical partial discharge inception voltage (PDIV) of the optimized PCB busbar is 1.7kVpeak with total charge <10pC. The power density of the DAHB converter is 1.8MVA/m 3 which is much higher than traditional two-stage industry products. The DAHB converter can be used as a building block for a 4.16kV/1MVA utility scale PV systems with input parallel and output series configuration.
Lightning induced damage is one of the major concerns in aircraft health monitoring. Such short-duration high voltages can cause significant damage to electronic devices. This paper presents a study on the effects of lightning injection on power metal-oxide semiconductor field effect transistors (MOSFETs). This approach consisted of pin-injecting lightning waveforms into the gate, drain and/or source of MOSFET devices while they were in the OFF-state. Analysis of the characteristic curves of the devices showed that for certain injection modes the devices can accumulate considerable damage rendering them inoperable. Early results demonstrate that a power MOSFET, even in its off-state, can incur considerable damage due to lightning pin injection, leading to significant deviation in its behavior and performance, and to possibly early device failures.
High efficiency, high density and galvanically isolated power converters are attractive for medium voltage high power applications. This paper presents a 1.5kV/200kW bidirectional Dual Active Bridge (DAB) converter using a newly developed 1.7kV SiC MOSFET module. The intended application is megawatt scale solid state transformer (SST) and 1500V PV inverter application using modular architecture. One novel model to estimate the turn-off loss using snubber capacitors is proposed and experimentally verified. An optimized PCB-based busbar design is introduced to reduce the voltage overshoot across the SiC device, making the design suitable for 1.5kVdc applications. The mechanism of how the optimized PCB-based busbar can reduce the voltage overshoot is quantitatively interpreted and experimentally verified. The DAB converter achieved an efficiency of 98.85% at 200kW and a maximum of 99.53% at 60kW. The maximum efficiency for series-resonant mode is 99.6% at 85kW and 99.3% at 200kW. The power density is 26W/inch3 (1.6MW/m3) which is much higher than traditional industry products.
Driver circuit generates rapid-voltage-transition pulses needed to switch high-power metal oxide/semiconductor field-effect transistor (MOSFET) modules rapidly between full "on" and full "off". Rapid switching reduces time of overlap between appreciable current through and appreciable voltage across such modules, thereby increasing power efficiency.
In these SEGR experiments, three identical-oxide MOSFET types were irradiated with six ions of significantly different ranges. Results show the prime importance of the total energy deposited in the epitaxial layer.
The use of MOSFETs in a high-frequency high-power dc-to-dc converter is investigated. Consideration is given to the phenomena associated with the paralleling of MOSFETs and to the effect of stray circuit inductances on the converter circuit performance. Analytical relationships between various time constants during the turning-on and turning-off intervals are derived which provide estimates of plateau and peak levels during these intervals.
In this paper, the concept and prototype of an aging detector for silicon carbide (SiC) power metal oxide semiconductor field effect transistor (MOSFET) are proposed and described. It leverages the resonant peak values of gate-source voltage at different instants during the switching transients to decode the change of multiple aging indicators, such as the increases of on-state resistance and threshold voltage. Modeling-based analysis is conducted to support the idea. The detector can be fully integrated into gate drivers without any additional connection to the power stage and is functional during normal power stage operation. A prototype unit was built, and preliminary tests were conducted to validate the idea and the practicality of the detector.
Single-event effect (SEE) and total ionizing dose (TID) test results are presented for various hardened and commercial power metal-oxide-semiconductor field effect transistors (MOSFETs), including vertical planar, trench, superjunction, and lateral process designs.
High current and voltage controlled remotely. Remote Power Conroller includes two series-connected banks of parallel-connected MOSFET's to withstand high current and voltage. Voltage sharing between switch banks, low-impedance, gate-drive circuits used. Provided controlled range for turn on. Individually trimmable to insure simultaneous switching within few nanoseconds during both turn on and turn off. Control circuit for each switch bank and over-current trip circuit float independently and supplied power via transformer T1 from inverter. Control of floating stages by optocouplers.
Planar, double-side cooled power modules are emerging in electric-drive inverters because of their low profile, better heat extraction, and lower package parasitic inductances. However, there is still concern about their reliability due to the rigid interconnection between the device chips and two substrates of the power module. In this paper, a porous interposer made of low-temperature sintered silver is introduced to reduce the thermo-mechanical stresses in the module. A double-side cooled half-bridge module consisting of two 1200 V, 149 A SiC MOSFETs was designed, fabricated, and characterized. By using the sintered-Ag instead of solid copper interposers, our simulation results showed that at a total power loss of 200 W, the thermo-mechanical stress at the most vulnerable interfaces (interposer-attach layer) was reduced by 42 % and in the SiC MOSFET by 50 % with a trade-off of only 3.6 % increase in junction temperature. The sintered-Ag interposers were readily fabricated into desired dimensions without post-machining and did not require any surface finishing for die-bonding and substrate interconnection by silver sintering. Here, the porous interposers were also deformable under a low force or pressure, which helped to accommodate chip thickness and/or substrate-to-substrate gap variations in the planar module structure, thus simplifying module fabrication. Experimental results on the electrical performance of the fabricated SiC modules validated the success of using the porous silver interposers for fabricating planar, double-side cooled power modules.