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Results for “Single Event Upset (SEU)”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2017

Heavy Ion and Proton-Induced Single Event Upset Characteristics of a 3D NAND Flash Memory

We evaluated the effects of heavy ion and proton irradiation for a 3D NAND flash. The 3D NAND showed similar single-event upset (SEU) sensitivity to a planar NAND of identical density in the multiple-cell level (MLC) storage mode. The 3D NAND showed significantly reduced SEU susceptibility in single-level-cell (SLC) storage mode. Additionally, the 3D NAND showed less multiple-bit upset susceptibility than the planar NAND, with fewer number of upset bits per byte and smaller cross sections overall. However, the 3D architecture exhibited angular sensitivities for both base and face angles, reflecting the anisotropic nature of the SEU vulnerability in space. Furthermore, the SEU cross section decreased with increasing fluence for both the 3D NAND and the Micron 16 nm planar NAND, which suggests that typical heavy ion test fluences will underestimate the upset rate during a space mission. These unique characteristics introduce complexity to traditional ground irradiation test procedures.

3D NAND Flash memory; radiation susceptibility; si↗
NASA NTRS2006

Radiation Tests on 2Gb NAND Flash Memories

We report on SEE and TID tests of highly scaled Samsung 2Gbits flash memories. Both in-situ and biased interval irradiations were used to characterize the response of the total accumulated dose failures. The radiation-induced failures can be categorized as followings: single event upset (SEU) read errors in biased and unbiased modes, write errors, and single-event-functional-interrupt (SEFI) failures.

NAND circuits↗
NASA NTRS2018

Xilinx Kintex-UltraScale Field Programmable Gate Array Single Event Effects (SEE) Heavy-Ion Test Report

This is an independent investigation that evaluates the single event destructive and transient susceptibility of the Xilinx Kintex-UltraScale device. Design/Device susceptibility is determined by monitoring the device under test (DUT) for Single Event Transient (SET) and Single Event Upset (SEU) induced faults by exposing the DUT to a heavy ion beam. Potential Single Event Latch-up (SEL) is monitored throughout heavy-ion testing by examining device current. This device does not have embedded mitigation. Hence, user implemented mitigation is investigated using Synopsys mitigation tools.

Single Event Transient (SET)↗
NASA NTRS2019

Microsemi RTG4 Rev C Field Programmable Gate Array Single Event Effects (SEE) Heavy-Ion Test Report

The goal of this study was to perform an independent investigation of single event destructive and transient susceptibility of the Microsemi RTG4 device. The devices under test were the Microsemi RTG4 field programmable gate array (FPGA) Rev C. The devices under test will be referenced as the DUT or RTG4 Rev C throughout this document. The DUT was configured to have various test structures that are geared to measure specific potential susceptibilities of the device. DesignDevice susceptibility was determined by monitoring the DUT for Single Event Transient (SET) and Single Event Upset (SEU) induced faults by exposing the DUT to a heavy ion beam. Potential Single Event Latch-up (SEL) was checked throughout heavy-ion testing by monitoring device current.

Field Programmable Gate Array (FPGA)↗
DOE OSTI2020

DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.

42 ENGINEERING↗
NASA NTRS2017

Single Event Effect Testing of the Micron MT46V128M8

The Micron MT46V128M8 was tested for single event effects (SEE) at the Texas AM University Cyclotron Facility (TAMU) in June of 2017. Testing revealed a sensitivity to device hang-ups classified as single event functional interrupts (SEFI) and possible soft data errors classified as single event upsets (SEU).

Single Event Functional Interrupts (SEFI)↗
NASA NTRS2001

A SEU-Hard Flip-Flop for Antifuse FPGAs

A single event upset (SEU)-hardened flip-flop has been designed and developed for antifuse Field Programmable Gate Array (FPGA) application. Design and application issues, testability, test methods, simulation, and results are discussed.

Katz, R.↗
NASA NTRS1993

Upper-Bound SEU Rates In Anisotropic Fluxes

Upper bounds on rates of single-event upsets (SEU's) in digital integrated circuits and other electronic devices exposed to anisotropic fluxes of energetic ionizing particles computed by use of improved method. Derived from simplified, worst-case mathematical models of charge-collecting volumes and physical phenomena in electronic devices.

Edmonds, Larry D.↗
NASA NTRS1997

Antifuse FPGA for Space Applications

This paper presents viewgraphs of Antifuse FPGA (Field Programmable Gate Array) for Space Applications. The topics include: 1) A32140DX TID Test; 2) A1280XL Proton Test; 3) SEU (Single Event Upsets) Rate Calculation; 4) Recent Products Test; 5) A1460A TID (Traveling Ionospheric Disturbances) Test; 6) I100 Proton Test; 7) 100/RHI100 SEU Test; 8) I100/RH100 TID Test; 9) A1020S TID Test; 10) TID Charge Pump Failure; 11) Radiation Testing; and SEE (Single Event Effects) Test Setup.

Wang, Jih-Jong↗
NASA NTRS1989

SEU In An Advanced Bipolar Integrated Circuit

Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

Zoutendyk, John A.↗
NASA NTRS1994

A method to compute SEU fault probabilities in memory arrays with error correction

With the increasing packing densities in VLSI technology, Single Event Upsets (SEU) due to cosmic radiations are becoming more of a critical issue in the design of space avionics systems. In this paper, a method is introduced to compute the fault (mishap) probability for a computer memory of size M words. It is assumed that a Hamming code is used for each word to provide single error correction. It is also assumed that every time a memory location is read, single errors are corrected. Memory is read randomly whose distribution is assumed to be known. In such a scenario, a mishap is defined as two SEU's corrupting the same memory location prior to a read. The paper introduces a method to compute the overall mishap probability for the entire memory for a mission duration of T hours.

Gercek, Gokhan↗
NASA NTRS1984

SEU of complementary GaAs static RAMs due to heavy ions

The first measurement of single event upset (SEU) for complementary GaAs static RAMs caused by heavy ions is reported. Upset cross-sections of the circuits for 28 MeV oxygen ions are reported as well as the linear energy transfer (LET) threshold established by using 170 MeV oxygen ions at various angles of beam incidence.

Zuleeg, R.↗
NASA NTRS1990

A new method for using Cf-252 in SEU testing

A system using Cf-252 and associated nuclear instrumentation has determined the single-event upset (SEU) cross section versus linear energy transfer (LET) curve for several 2K x 8 static random access memories (SRAMs). The Cf-252 fission fragments pass through a thin-film organic scintillator detector (TFD) on the way to the device under test (DUT). The TFD provides energy information for each transiting fragment. Data analysis provides the energy of the individual ion responsible for each SEU; thus, separate upset cross sections can be developed for different energy and mass regions of the californium spectrum. This californium-based device is quite small and fits onto a bench top. It provides a convenient and inexpensive supplement or alternative to accelerator and high-altitude/space SEU testing.

Costantine, A.↗
NASA NTRS2017

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

Field Programmable Gate Array (FPGA); Triple Modul↗
NASA NTRS2016

Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets in a NAND Flash Memory

We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found that the single-event upset (SEU) cross section varied inversely with cumulative fluence. We attribute the effect to the variable upset sensitivities of the memory cells. Furthermore, the effect impacts only single cell upsets in general. The rate of multiple-bit upsets remained relatively constant with fluence. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, traditional SEE testing techniques may underestimate the on-orbit event rate for a device with variable upset sensitivity.

NAND flash memory↗
NASA NTRS1988

Estimating Rates Of Single-Event Upsets

Mathematical model yields estimates of upper and lower bounds on rates of single-event upsets (SEU's) in logic circuits. SEU's are reversible changes in logic states, caused by single high-energy ions. Energetic ions passed through device along tracks perpendicular to surface, to determine parameters of model. Used to estimate rates caused by ions of various energies incident at arbitrary angles. Useful in design of integrated circuits as high-density memories for minimal susceptibility to bit errors.

Zoutendyk, John A.↗
NASA NTRS1992

Low power SEU immune CMOS memory circuits

The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

Liu, M. N.↗