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Results for “Stacked memory”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Stacking-engineered ferroelectricity in bilayer boron nitride

Stacking a ferroelectric Properties of layered van der Waals structures can depend sensitively on the stacking arrangement of constituent layers. This phenomenon has been exploited to engineer superconducting, correlated insulator, and magnetic states. Two groups now show that ferroelectricity can also be engineered through stacking: Parallel-stacked bilayers of hexagonal boron nitride exhibit ferroelectric switching even though the bulk material is not ferroelectric (see the Perspective by Tsymbal). To explore these phenomena, Yasuda et al. used transport measurements, whereas Vizner Stern et al. focused on atomic force microscopy. Science , abd3230 and abe8177, this issue p. 1458 and p. 1462 ; see also abi7296, p. 1389

Science & Technology - Other Topics↗
DOE OSTI2015

Direct observation of conductive filament formation in Alq3 based organic resistive memories

This work explores resistive switching mechanisms in non-volatile organic memory devices based on tris(8-hydroxyquinolie)aluminum (Alq{sub 3}). Advanced characterization tools are applied to investigate metal diffusion in ITO/Alq{sub 3}/Ag memory device stacks leading to conductive filament formation. The morphology of Alq{sub 3}/Ag layers as a function of the metal evaporation conditions is studied by X-ray reflectivity, while depth profile analysis with X-ray photoelectron spectroscopy and time-of-flight secondary ion mass spectrometry is applied to characterize operational memory elements displaying reliable bistable current-voltage characteristics. 3D images of the distribution of silver inside the organic layer clearly point towards the existence of conductive filaments and allow for the identification of the initial filament formation and inactivation mechanisms during switching of the device. Initial filament formation is suggested to be driven by field assisted diffusion of silver from abundant structures formed during the top electrode evaporation, whereas thermochemical effects lead to local filament inactivation.

36 MATERIALS SCIENCE↗
DOE OSTI2019

Field-free Magnetization Switching by Utilizing the Spin Hall Effect and Interlayer Exchange Coupling of Iridium

Magnetization switching by spin-orbit torque (SOT) via spin Hall effect represents as a competitive alternative to that by spin-transfer torque (STT) used for magnetoresistive random access memory (MRAM), as it doesn’t require high-density current to go through the tunnel junction. For perpendicular MRAM, however, SOT driven switching of the free layer requires an external in-plane field, which poses limitation for viability in practical applications. Here we demonstrate field-free magnetization switching of a perpendicular magnet by utilizing an Iridium (Ir) layer. The Ir layer not only provides SOTs via spin Hall effect, but also induce interlayer exchange coupling with an in-plane magnetic layer that eliminates the need for the external field. Such dual functions of the Ir layer allows future build-up of magnetoresistive stacks for memory and logic applications. Experimental observations show that the SOT driven field-free magnetization reversal is characterized as domain nucleation and expansion. Micromagnetic modeling is carried out to provide in-depth understanding of the perpendicular magnetization reversal process in the presence of an in-plane exchange coupling field.

Science & Technology - Other Topics↗
NASA NTRS1996

Semiconductor Cubing

Through Goddard Space Flight Center and Jet Propulsion Laboratory Small Business Innovation Research contracts, Irvine Sensors developed a three-dimensional memory system for a spaceborne data recorder and other applications for NASA. From these contracts, the company created the Memory Short Stack product, a patented technology for stacking integrated circuits that offers higher processing speeds and levels of integration, and lower power requirements. The product is a three-dimensional semiconductor package in which dozens of integrated circuits are stacked upon each other to form a cube. The technology is being used in various computer and telecommunications applications.

Source record↗
NASA NTRS1991

High density packaging and interconnect of massively parallel image processors

This paper presents conceptual designs for high density packaging of parallel processing systems. The systems fall into two categories: global memory systems where many processors are packaged into a stack, and distributed memory systems where a single processor and many memory chips are packaged into a stack. Thermal behavior and performance are discussed.

Carson, John C.↗
DOE OSTI2020

Method and apparatus for temperature-gradient aware data-placement for 3D stacked DRAMs

A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2013

Forced Ion Migration for Chalcogenide Phase Change Memory Device

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

Campbell, Kristy A↗
NASA NTRS2011

Forced ion migration for chalcogenide phase change memory device

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more that two data states.

Campbell, Kristy A.↗
NASA NTRS2012

Forced ion migration for chalcogenide phase change memory device

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

Campbell, Kristy A.↗
NASA NTRS1995

Vertical bloch line memory

A new read gate design for the vertical Bloch line (VBL) memory is disclosed which offers larger operating margin than the existing read gate designs. In the existing read gate designs, a current is applied to all the stripes. The stripes that contain a VBL pair are chopped, while the stripes that do not contain a VBL pair are not chopped. The information is then detected by inspecting the presence or absence of the bubble. The margin of the chopping current amplitude is very small, and sometimes non-existent. A new method of reading Vertical Bloch Line memory is also disclosed. Instead of using the wall chirality to separate the two binary states, the spatial deflection of the stripe head is used. Also disclosed herein is a compact memory which uses vertical Bloch line (VBL) memory technology for providing data storage. A three-dimensional arrangement in the form of stacks of VBL memory layers is used to achieve high volumetric storage density. High data transfer rate is achieved by operating all the layers in parallel. Using Hall effect sensing, and optical sensing via the Faraday effect to access the data from within the three-dimensional packages, an even higher data transfer rate can be achieved due to parallel operation within each layer.

Katti, Romney R.↗
DOE OSTI2020

Memory Analysis Tool

This tool traces all memory accesses to stack (static allocation) and heap (dynamic allocation) on a trace run in a particular hardware and then estimates execution time on given arbitrary hardware configurations for hardware design space exploration. It can also compute memory access statistics, such as reuse distance.

Sato, Kento↗
DOE OSTI2020

Stacking faults and alternate crystal structures for the shape-memory alloy NiTi

Here, we use ab initio calculations to study the role of stacking faults in connecting the high-temperature B2 and the theoretically predicted low-temperature B33 NiTi phases. In contrast with prior work, we describe the B 2 → B 33 phase transformation in terms of alternate bilayer shifts by 1 2 [100] on the ( 011 ) B 2 plane, obtaining a viable pathway; the same mechanism could also work with the B19 parent phase. We then examine B33-like structures built from alternate stacking sequences of B19 bilayers, constructed to have monoclinic tilt angles close to the experimentally reported NiTi B19' martensite, and find four low-energy stacking-fault variants with energies 5.8–8.5 meV/atom above the calculated B19' martensite structure, suggesting that such structures might appear as a part of the NiTi martensite phase at low temperatures. Investigating further the occurrence of specific coordinated planar shifts in NiTi systems, we report a dynamically stable NiTi B27 phase and find that it is only 1.2 meV/atom above the calculated B33 ground-state structure, thus having a potential to also play a role in NiTi martensitic phase transformation.

36 MATERIALS SCIENCE↗
NASA NTRS2002

Validation of an SEU simulation technique for a complex processor: PowerPC7400

Published data on the processors sensitivites with respect to SEU is generally obtained from radiation ground testing during which the program is executed by the DUT consists in the sequential inspection of each of the processor memory cells accessible to the user, through the execution of a suitable instruction sequence. In such programs, so-called static tests, typically considered memory cells are general-purpose registers, special registers (program counter, stack pointer...) and internal memory. Nevertheless, the register use and duty cycle of the final application will be very different, including using instructions no in the static tests and disturbing other potential SEU targets. The ideal would be the use of the final application program for the radiation ground testing, but generally this program is either unknown or unavailable when the qualification testing is performed on candidate circuits to space projects.

Radiation↗
DOE OSTI2022

Software Verification Toolkit (SVT): Survey on Available Software Verification Tools and Future Direction

Writing software is difficult. However, writing complex, well tested and designed, and functionally correct software is incredibly difficult. An entire field of study is devoted to the validation and verification of software to address this problem, and in this paper we analyze the landscape of currently available third party software. We have divided our analyses into three separate subsections with regards to software validation: formal methods, static analysis, and test generation. Formal verification is the most complex method in which to validate software correctness, but also the most thorough as it truly validates the mathematical validity of the source code. Static analysis generally is relegated to abstract syntax tree traversal techniques to find errors related to faulty software such as memory leaks or stack overflow issues. Automatic test generation is similar in implementation to static analysis, but pushes a bit further in verifying the boundedness of function inputs and outputs with regards to annotated or parsed criteria. The crux of this report is to analyze and describe the software tools that implement these techniques to validate and verify software. Pros and cons related to installation, utilization, and capabilities of the frameworks are described, and reproducible examples are provided with a focus on usability. The initial survey concluded that the most interesting tools of note are Z3, Isabelle/HOL, and TLA+ with regards to formal verification; and Infer, Frama-C, and SonarQube with regards to static analysis. With these tools in mind, a final conjecture is provided that describes future avenues of utilizing these tools for developing a verification framework to assist in validating existing software at Sandia National Laboratories.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Fixing Amdahl's Law within the Limits of Accelerated Systems: FALLACY

Closeout report for FALLACY project. The performance of Data Model Convergence Initiative (DMC) applications on parallel machines is far below the limit set by Amdahl’s law. Whether the machine is based on many-core, GPUs, FPGAs, or a heterogeneous combination, usually the most significant bottleneck is accessing data from the memory system. Aligning with DMC’s HW/architecture thrust, this project developed a set of memory-centric tools called ‘MemGaze’ that inform the HW/SW stack about an application’s memory behavior, including data access latency and diagnosing poor data layout and data composition. Our approach uses architectural modeling and analysis of workload data accesses.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Investigating permafrost carbon dynamics in Alaska with artificial intelligence

Abstract Positive feedbacks between permafrost degradation and the release of soil carbon into the atmosphere impact land–atmosphere interactions, disrupt the global carbon cycle, and accelerate climate change. The widespread distribution of thawing permafrost is causing a cascade of geophysical and biochemical disturbances with global impacts. Currently, few earth system models account for permafrost carbon feedback (PCF) mechanisms. This research study integrates artificial intelligence (AI) tools and information derived from field-scale surveys across the tundra and boreal landscapes in Alaska. We identify and interpret the permafrost carbon cycling links and feedback sensitivities with GeoCryoAI, a hybridized multimodal deep learning (DL) architecture of stacked convolutionally layered, memory-encoded recurrent neural networks (NN). This framework integratesin-situmeasurements and flux tower observations for teacher forcing and model training. Preliminary experiments to quantify, validate, and forecast permafrost degradation and carbon efflux across Alaska demonstrate the fidelity of this data-driven architecture. More specifically, GeoCryoAI logs the ecological memory and effectively learns covariate dynamics while demonstrating an aptitude to simulate and forecast PCF dynamics—active layer thickness (ALT), carbon dioxide flux (CO 2 ), and methane flux (CH 4 )—with high precision and minimal loss (i.e. ALT RMSE : 1.327 cm [1969–2022]; CO 2 RMSE : 0.697µmolCO 2 m −2 s −1 [2003–2021]; CH 4 RMSE : 0.715 nmolCH 4 m −2 s −1 [2011–2022]). ALT variability is a sensitive harbinger of change, a unique signal characterizing the PCF, and our model is the first characterization of these dynamics across space and time.

Environmental Sciences & Ecology↗
NASA NTRS1992

Processor architecture and data buffering

A set of architectures from three major architecture families: stack, register, and memory-to-memory is discussed. It is shown that scalable architectures are not applicable for low-density technologies because they require at least 32 words of local memory. Software support is shown to be capable of bridging the performance gap between scalable and nonscalable architectures. A register architecture with 32 words of local memory allocated interprocedurally outperforms scalable architectures with equal sizes local memories and even some with larger size local memories. The performance advantage of unscalable architectures becomes significant when in addition to quality compile-time support, a small cache is added to an unscalable architecture. A 32-register architecture with 512 byte cache executes 20 percent less cycles when compared with an 8-set multiple overlapping set organization.

Mulder, Hans↗
NASA NTRS2005

Temperature-Controlled Clamping and Releasing Mechanism

A report describes the development of a mechanism that automatically clamps upon warming and releases upon cooling between temperature limits of approx. =180 K and approx. =293 K. The mechanism satisfied a need specific to a program that involved repeated excursions of a spectrometer between a room-temperature atmospheric environment and a cryogenic vacuum testing environment. The mechanism was also to be utilized in the intended application of the spectrometer, in which the spectrometer would be clamped for protection during launch of a spacecraft and released in the cold of outer space to allow it to assume its nominal configuration for scientific observations. The mechanism is passive in the sense that its operation does not depend on a control system and does not require any power other than that incidental to heating and cooling. The clamping and releasing action is effected by bolt-preloaded stacks of shape-memory-alloy (SMA) cylinders. In designing this mechanism, as in designing other, similar SMA mechanisms, it was necessary to account for the complex interplay among thermal expansion, elastic and inelastic deformation under load, and SMA thermomechanical properties.

Rosing, David↗