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LISA Pathfinder
USA Pathfinder is a space mission dedicated to demonstrating technology for the Laser Interferometer Space Antenna (LISA). LISA is a joint ESA/NASA mission to detect low-frequency gravitational waves on the 0.0001 to 0.1 Hz frequency band. LISA is expected to observe 100's of merging massive black hole binaries out z-15, tens of thousands of close compact binary systems in the Milky Way, merging intermediate-mass black hole binaries, tens of stellar-mass black holes falling into supermassive black holes in galactic centers, and possibly other exotic sources. Several critical LISA technologies have not been demonstrated at the requisite level of performance. In spaceflight, and some fight hardware cannot be tested in a 1-g environment. Hence, the LISA Pathfinder mission is being implemented to demonstrate these critical LISA technologies in a relevant flight environment. LISA Pathfinder mimics one arm of the LISA constellation by shrinking the 5-million-kilometer armlength down to a few tens of centimeters. The experimental concept is to measure the relative separation between two test masses nominally following their own geodesics, and thereby determine the relative residual acceleration between them near 1 mHz, about a decade above the lowest frequency required by LISA. To implement such a concept, disturbances on the test masses must be kept very small by many design features, but chiefly by "drag-free" flight. A drag-free spacecraft follows a free-falling test mass which it encloses, but has no mechanical connection to. The spacecraft senses it's orientation and separation with respect to the proof mass, and its propulsion system is commanded to keep the spacecraft centered about the test mass. Thus, the spacecraft shields the test mass from most external influences, and minimizes the effect of force gradients arising from the spacecraft, and acting on the test mass. LISA Pathfinder will compare the geodesic of one test mass against that of the other. Only a metrology system based on interferometry can achieve the displacement sensitivity. Interferometers monitor the separation of both test masses with a sensitivity comparable to that required by LISA, and using the same technologies. LISA Pathfinder is scheduled to be launched in the first half of 1020 to a Lissajous orbit around the first Sun-Earth Lagrange point, L1. In addition to a complete European technology package (the LISA Technology Package, or LTP), LISA Pathfinder will also carry thrusters and software, known as ST-7, a part of NASA's New Millennium Program.
Technical Challenges in Reliable Microelectronics Packaging of Microelectromechanical Systems (MEMS) for Space Applications
MEMS have shown a significant promise in the last decade for a variety of applications such as air-bag, pressure sensors, accelerometer, microgyro, chemical sensors, artificial nose, etc. Standard semiconductor microelectronics packaging needs the integrated circuits (IC) to be protected from the harsh environment, and provide electrical communication with the other parts of the circuit, facilitate thermal dissipation efficiently, and impart mechanical strength to the silicon die. Microelectronics packaging involves wafer dicing, bonding, lead attachment, encapsulation to protect from the environment, electrical integrity, and package leak tests to assure the reliable IC packaging technology. Active elements or microstructures in MEMS devices often interfaces with the hostile environment where packaging leak tests and testing of such devices using chemical and mechanical parameters will be very difficult and expensive. Packaging of MEMS is significantly complex as they serve to protect from the environment and microstructures interact with the same environment to measure or affect the desired physical or chemical parameters. The most of the silicon circuitry is sensitive to temperature, moisture, magnetic field, light, and electromagnetic interference. The package must then protect the on-board silicon circuitry while simultaneously exposing the microsensor to the effect it measures to assure the packaging technology of MEMS. MEMS technology has a major application in developing a microspacecraft for space systems provided reliability of MEMS packaging technology is sufficiently addressed. This MEMS technology would eventually miniaturize many of the components of the spacecraft to reach the NASA's goal by building faster, cheaper, better, smaller spacecraft to explore the space more effectively. This paper discusses the latest developments in the MEMS technology and challenging technical issues in the packaging of hermetically sealed and non-hermetically sealed MEMS sensor devices for microspacecraft applications.
Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap
The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in the area of microelectronics packaging, this report presents only a number of key packaging technologies detailed in three industry roadmaps for conventional microelectronics and a more recently introduced roadmap for organic and printed electronics applications. The topics for each category were down-selected by reviewing the 2012 reports of the International Technology Roadmap for Semiconductor (ITRS), the 2013 roadmap reports of the International Electronics Manufacturing Initiative (iNEMI), the 2013 roadmap of association connecting electronics industry (IPC), the Organic Printed Electronics Association (OE-A). The report also summarizes the results of numerous articles and websites specifically discussing the trends in microelectronics packaging technologies.
System Miniaturization Via Heterogeneous Integration of Electronic Devices for Deep Space Missions
The scientific devices designed for each of the Outer Planets Program Focuses will likely be groundbreaking not only with respect to their scientific role but also regarding the electronics required to perform such investigations. In the past, the performance of packaged electronics was limited by the components themselves, with minimal influence of the packaging technology. The rapid development of integrated circuit technology, however, has drastically increased the importance of packaging technology in the ultimate performance of devices. If not carefully considered in the overall design, the packaging may become the limiting factor in the operation of the system. Although industry is responsible for several significant accomplishments in the field of electronics packaging, deep space/outer planet missions must take into account additional requirements such as extremely low temperatures, high radiation levels, hermetic sealing, and severe size and weight limitations. Therefore, the present investigation has been designed to meet the needs of NASA's sensor intensive outer planets program by combining (using flip chip technology) an array of devices (including analog, digital, power volt-age, passives, and MEMS) into a miniaturized heterogeneous system and utilizing optical buses to enable autonomy. Additional information is contained in the original extended abstract.
Cold Survivable Electronics Motor Control Law Implementation
For the last seven years JPL has been developing motor control electronics for use on future missions to extreme environments such as Europa and Mars. The packaging technology developed will allow the electronics to survive the extremes seen on the surface. This packaging technology allows us to package everything to control a number of motors on a single card including the closed loop control. In order to improve the performance of the motor control we have developed FPGA code to close the position, velocity and current control loops of the motor controller. This code allowed for a significant improvement in loop rate allowing the control of the motors to be more accurate. This allows for more accurate control of descent engines, more precise control of robotic arm motors. In this paper we will present the design of the control algorithm, the performance of the sensors and the test results of the resulting system.
High-Temperature, Wirebondless, Ultracompact Wide Bandgap Power Semiconductor Modules
Silicon carbide (SiC) and other wide bandgap semiconductors offer great promise of high power rating, high operating temperature, simple thermal management, and ultrahigh power density for both space and commercial power electronic systems. However, this great potential is seriously limited by the lack of reliable high-temperature device packaging technology. This Phase II project developed an ultracompact hybrid power module packaging technology based on the use of double lead frames and direct lead frame-to-chip transient liquid phase (TLP) bonding that allows device operation up to 450 degC. The new power module will have a very small form factor with 3-5X reduction in size and weight from the prior art, and it will be capable of operating from 450 degC to -125 degC. This technology will have a profound impact on power electronics and energy conversion technologies and help to conserve energy and the environment as well as reduce the nation's dependence on fossil fuels.
Enabling More than Moore: Accelerated Reliability Testing and Risk Analysis for Advanced Electronics Packaging
For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk.
Multispectral Linear Array detector technology
The Multispectral Linear Array (MLA) program sponsored by NASA has the aim to extend space-based remote sensor capabilities. The technology development effort involves the realization of very large, all-solid-state, pushbroom focal planes. The pushbroom, staring focal planes will contain thousands of detectors with the objective to provide two orders of magnitude improvement in detector dwell time compared to present Landsat mechanically scanned systems. Attenton is given to visible and near-infrared sensor development, the shortwave infrared sensor, aspects of filter technology development, the packaging concept, and questions of system performance. First-sample, four-band interference filters have been fabricated successfully, and a hybrid packaging technology is being developed.
NASA Electronic Parts and Packaging Program
NEPP program objectives are to: (1) Access the reliability of newly available electronic parts and packaging technologies for usage on NASA projects through validations, assessments, and characterizations, and the development of test methods/tools; (2)Expedite infusion paths for advanced (emerging) electronic parts and packaging technologies by evaluations of readiness for manufacturability and project usage consideration; (3) Provide NASA projects with technology selection, application, and validation guidelines for electronic parts and packaging hardware and processes; nd (4) Retain and disseminate electronic parts and packaging quality assurance, reliability validations, tools, and availability information to the NASA community.
Advanced Failure Determination Measurement Techniques Used in Thermal Fatigue Life Testing of Electronic Packaging
Thermal fatigue life testing of various electronic packaging technologies is being performed by the Reliability Technology Group at the Jet Propulsion Laboratory. These testing efforts are in progress to improve uderstanding of the reliability issues associated with low volume packaging technologies for space applications and to develop qualification and acceptance approaches for these technologies. The work described here outlines the electrical failure detection techniques used during testing by documenting the circuits and components used to make these measurements, the sensitivity of the measurements, and the applicability of each specific measurement.
Conceive, Believe and Achieve; A Path to Miniaturization, COTS Infusion, and Size Weight and Power Realization for Flight
JPL along with other aerospace agencies such as the US Air Force Space Pro-grams and a packaging technology innovator, i3 Electronics, Inc., are evaluating the use of state-of-the-art (SOA) commercial off-the-shelf (COTS) and alternative packaging technologies for future high performance and high reliability space applications. Utilization of SOA COTS technologies have resulted in large scale reduction in electronics volume, weight, power, cost and schedule with outstanding electrical performance and high reliability. We will share JPL’s joint design, architectural approach, alternative substrate materials selection, associated processes, and mission assurance role in identifying reliability and qualification risks, as part of the three year Heterogeneous Packaging/Device Integration effort under the guidance and leadership of JPL’s Mission Assurance Directorate.
Issues in the development of a 10 MBPS K=15 Viterbi decoder
The NMSU Telemetry Center, in collaboration with the NASA Microelectronics Center (MRC) at UNM, has completed a study of the feasibility of building a constraint length 15, rate 1/2 Viterbi Decoder (or BVD) to operate at a rate of 10 Mbps. The BVD, if built, would make TDRSS more accessible to all users, small satellites in particular, by providing an additional 2 dB of link margin, relative to the use of the standard constraint length 7 decoder. The study included the following: review of the 1 Mbps BVD built by the Jet Propulsion Laboratory (JPL), currently the only BVD in existence; development of Specifications for the basic processing unit of the BVD (MRC); analytical Determination of performance of large constraint length convolutional codes; investigation of the impact of processor design on the overall system design; and two feasible packaging technologies, proposed by Cincinnati Electronics of Ohio. It was concluded that while the construction of the BVD is feasible, it will require the most advanced packaging technology currently available, and that the project would be best accomplished in an industrial facility. While the size, complexity, and power requirements of the BVD will be extreme, these will impact only the ground station. The spacecraft will incur a minor change in the encoder design, and the increased coding gain will allow a satellite to operate with a smaller antenna.
JTEC Panel report on electronic manufacturing and packaging in Japan
This report summarizes the status of electronic manufacturing and packaging technology in Japan in comparison to that in the United States, and its impact on competition in electronic manufacturing in general. In addition to electronic manufacturing technologies, the report covers technology and manufacturing infrastructure, electronics manufacturing and assembly, quality assurance and reliability in the Japanese electronics industry, and successful product realization strategies. The panel found that Japan leads the United States in almost every electronics packaging technology. Japan clearly has achieved a strategic advantage in electronics production and process technologies. Panel members believe that Japanese competitors could be leading U.S. firms by as much as a decade in some electronics process technologies.
Electronic manufacturing and packaging in Japan
This report summarizes the status of electronic manufacturing and packaging technology in Japan in comparison to that in the United States, and its impact on competition in electronic manufacturing in general. In addition to electronic manufacturing technologies, the report covers technology and manufacturing infrastructure, electronics manufacturing and assembly, quality assurance and reliability in the Japanese electronics industry, and successful product realization strategies. The panel found that Japan leads the United States in almost every electronics packaging technology. Japan clearly has achieved a strategic advantage in electronics production and process technologies. Panel members believe that Japanese competitors could be leading U.S. firms by as much as a decade in some electronics process technologies. Japan has established this marked competitive advantage in electronics as a consequence of developing low-cost, high-volume consumer products. Japan's infrastructure, and the remarkable cohesiveness of vision and purpose in government and industry, are key factors in the success of Japan's electronics industry. Although Japan will continue to dominate consumer electronics in the foreseeable future, opportunities exist for the United States and other industrial countries to capture an increasingly large part of the market. The JTEC panel has identified no insurmountable barriers that would prevent the United States from regaining a significant share of the consumer electronics market; in fact, there is ample evidence that the United States needs to aggressively pursue high-volume, low-cost electronic assembly, because it is a critical path leading to high-performance electronic systems.
500 C Electronic Packaging and Dielectric Materials for High Temperature Applications
High-temperature environment operable sensors and electronics are required for exploring the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high temperature electronics, and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by these high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed. High-temperature environment operable sensors and electronics are required for probing the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and eventual applications of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high electronics and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed.
Chip-on-Board Technology 1996 Year-end Report (Design, Manufacturing, and Reliability Study)
The major impetus for flight qualifying Chip-On-Board (COB) packaging technology is the shift in emphasis for space missions to smaller, better, and cheaper spacecraft and satellites resulting from the NASA New Millenium initiative and similar requirements in DoD-sponsored programs. The most important benefit that can potentially be derived from miniaturizing spacecraft and satellites is the significant cost saving realizable if a smaller launch vehicle may be employed. Besides the program cost saving, there are several other advantages to building COB-based space hardware. First, once a well-controlled process is established, COB can be low cost compared to standard Multi-Chip Module (MCM) technology. This cost competitiveness is regarded as a result of the generally greater availability and lower cost of Known Good Die (KGD). Coupled with the elimination of the first level of packaging (chip package), compact, high-density circuit boards can be realized with Printed Wiring Boards (PWB) that can now be made with ever-decreasing feature size in line width and via hole. Since the COB packaging technique in this study is based mainly on populating bare dice on a suitable multi-layer laminate substrate which is not hermetically sealed, die coating for protection from the environment is required. In recent years, significant improvements have been made in die coating materials which further enhance the appeal of COB. Hysol epoxies, silicone, parylene and silicon nitride are desirable because of their compatible Thermal Coefficient of Expansion (TCE) and good moisture resistant capability. These die coating materials have all been used in the space and other industries with varying degrees of success. COB technology, specifically siliconnitride coated hardware, has been flown by Lockheed on the Polar satellite. In addition, DARPA has invested a substantial amount of resources on MCM and COB-related activities recently. With COB on the verge of becoming a dominant player in DoD programs, DARPA is increasing its support of the availability of KGDs which will help decrease their cost. Aside from the various major developments and trends in the space and defense industries that are favorable to the acceptance and widespread use of'COB packaging technology, implementing COB can be appealing in other aspects. Since the interconnection interface is usually the weak link in a system, the overall circuit or system reliability may actually be improved because of the elimination of a level of interconnect/packaging at the chip. With COB, mixing packaging technologies is possible. Because some devices are only available in commercial plastic packages, populating a multi-layer laminate substrate with both bare dice and plastic-package parts is inevitable. Another attractive feature of COB is that re-workability is possible if die coating is applied only on the die top. This method allows local replacement of individual dice that were found to be defective instead of replacing an entire board. In terms of thermal management, unpackaged devices offer a shorter thermal resistance path than their packaged counterparts thereby improving thermal sinking and heat removal from the parts.