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NASA NTRS2003

Packaging Technology Designed, Fabricated, and Assembled for High-Temperature SiC Microsystems

A series of ceramic substrates and thick-film metalization-based prototype microsystem packages designed for silicon carbide (SiC) high-temperature microsystems have been developed for operation in 500 C harsh environments. These prototype packages were designed, fabricated, and assembled at the NASA Glenn Research Center. Both the electrical interconnection system and the die-attach scheme for this packaging system have been tested extensively at high temperatures. Printed circuit boards used to interconnect these chip-level packages and passive components also are being fabricated and tested. NASA space and aeronautical missions need harsh-environment, especially high-temperature, operable microsystems for probing the inner solar planets and for in situ monitoring and control of next-generation aeronautical engines. Various SiC high-temperature-operable microelectromechanical system (MEMS) sensors, actuators, and electronics have been demonstrated at temperatures as high as 600 C, but most of these devices were demonstrated only in the laboratory environment partially because systematic packaging technology for supporting these devices at temperatures of 500 C and beyond was not available. Thus, the development of a systematic high-temperature packaging technology is essential for both in situ testing and the commercialization of high-temperature SiC MEMS. Researchers at Glenn developed new prototype packages for high-temperature microsystems using ceramic substrates (aluminum nitride and 96- and 90-wt% aluminum oxides) and gold (Au) thick-film metalization. Packaging components, which include a thick-film metalization-based wirebond interconnection system and a low-electrical-resistance SiC die-attachment scheme, have been tested at temperatures up to 500 C. The interconnection system composed of Au thick-film printed wire and 1-mil Au wire bond was tested in 500 C oxidizing air with and without 50-mA direct current for over 5000 hr. The Au thick-film metalization-based wirebond electrical interconnection system was also tested in an extremely dynamic thermal environment to assess thermal reliability. The I-V curve1 of a SiC high-temperature diode was measured in oxidizing air at 500 C for 1000 hr to electrically test the Au thick-film material-based die-attach assembly.

Chen, Liang-Yu↗

NASA NTRS2003

Microelectromechanical Systems (MEMS) Broadband Light Source Developed

A miniature, low-power broadband light source has been developed for aerospace applications, including calibrating spectrometers and powering miniature optical sensors. The initial motivation for this research was based on flight tests of a Fabry-Perot fiberoptic temperature sensor system used to detect aircraft engine exhaust gas temperature. Although the feasibility of the sensor system was proven, the commercial light source optically powering the device was identified as a critical component requiring improvement. Problems with the light source included a long stabilization time (approximately 1 hr), a large amount of heat generation, and a large input electrical power (6.5 W). Thus, we developed a new light source to enable the use of broadband optical sensors in aerospace applications. Semiconductor chip-based light sources, such as lasers and light-emitting diodes, have a relatively narrow range of emission wavelengths in comparison to incandescent sources. Incandescent light sources emit broadband radiation from visible to infrared wavelengths; the intensity at each wavelength is determined by the filament temperature and the materials chosen for the filament and the lamp window. However, present commercial incandescent light sources are large in size and inefficient, requiring several watts of electrical power to obtain the desired optical power, and they emit a large percentage of the input power as heat that must be dissipated. The miniature light source, developed jointly by the NASA Glenn Research Center, the Jet Propulsion Laboratory, and the Lighting Innovations Institute, requires one-fifth the electrical input power of some commercial light sources, while providing similar output light power that is easily coupled to an optical fiber. Furthermore, it is small, rugged, and lightweight. Microfabrication technology was used to reduce the size, weight, power consumption, and potential cost-parameters critical to future aerospace applications. This chip-based light source has the potential for monolithic fabrication with on-chip drive electronics. Other uses for these light sources are in systems for vehicle navigation, remote sensing applications such as monitoring bridges for stress, calibration sources for spectrometers, light sources for space sensors, display lighting, addressable arrays, and industrial plant monitoring. Two methods for filament fabrication are being developed: wet-chemical etching and laser ablation. Both yield a 25-mm-thick tungsten spiral filament. The proof-of-concept filament shown was fabricated with the wet etch method. Then it was tested by heating it in a vacuum chamber using about 1.25 W of electrical power; it generated bright, blackbody radiation at approximately 2650 K. The filament was packaged in Glenn's clean-room facilities. This design uses three chips vacuum-sealed with glass tape. The bottom chip consists of a reflective film deposited on silicon, the middle chip contains a tungsten filament bonded to silicon, and the top layer is a transparent window. Lifetime testing on the package will begin shortly. The emitted optical power is expected to be approximately 1.0 W with the spectral peak at 1.1 mm.

Tuma, Margaret L.↗

NASA NTRS2010

System on a Chip (SoC) Overview

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

LaBel, Kenneth A.↗

NASA NTRS2001

Performance of High-Speed PWM Control Chips at Cryogenic Temperatures

The operation of power electronic systems at cryogenic temperatures is anticipated in many NASA space missions such as planetary exploration and deep space probes. In addition to surviving the space hostile environment, electronics capable of low temperature operation would contribute to improving circuit performance, increasing system efficiency, and reducing development and launch costs. As part of the NASA Glenn Low Temperature Electronics Program, several commercial high-speed Pulse Width Modulation (PWM) chips have been characterized in terms of their performance as a function of temperature in the range of 25 to -196 C (liquid nitrogen). These chips ranged in their electrical characteristics, modes of control, packaging options, and applications. The experimental procedures along with the experimental data obtained on the investigated chips are presented and discussed.

Elbuluk, Malik E.↗

NASA NTRS1998

GSFC Cutting Edge Avionics Technologies for Spacecraft

With the launch of NASA's first fiber optic bus on SAMPEX in 1992, GSFC has ushered in an era of new technology development and insertion into flight programs. Predating such programs the Lewis and Clark missions and the New Millenium Program, GSFC has spearheaded the drive to use cutting edge technologies on spacecraft for three reasons: to enable next generation Space and Earth Science, to shorten spacecraft development schedules, and to reduce the cost of NASA missions. The technologies developed have addressed three focus areas: standard interface components, high performance processing, and high-density packaging techniques enabling lower cost systems. To realize the benefits of standard interface components GSFC has developed and utilized radiation hardened/tolerant devices such as PCI target ASICs, Parallel Fiber Optic Data Bus terminals, MIL-STD-1773 and AS1773 transceivers, and Essential Services Node. High performance processing has been the focus of the Mongoose I and Mongoose V rad-hard 32-bit processor programs as well as the SMEX-Lite Computation Hub. High-density packaging techniques have resulted in 3-D stack DRAM packages and Chip-On-Board processes. Lower cost systems have been demonstrated by judiciously using all of our technology developments to enable "plug and play" scalable architectures. The paper will present a survey of development and insertion experiences for the above technologies, as well as future plans to enable more "better, faster, cheaper" spacecraft. Details of ongoing GSFC programs such as Ultra-Low Power electronics, Rad-Hard FPGAs, PCI master ASICs, and Next Generation Mongoose processors.

Luers, Philip J.↗

NASA NTRS2019

ISSI IS46DR16640B-25DBA25 DDR2 SDRAM Total Ionizing Dose Characterization Test Report

The purpose of this testing is to characterize the ISSI IS46DR16640B-25DBA25 parameter degradation for total dose response. This test’s purpose is to evaluate and compare lot date codes for sensitivity. In the test, the device is exposed to both low dose and high dose rate (HDR) irradiations using gamma radiation. Device parameters such as leakage currents, quantity of upset bits or addresses, and overall chip and die health are investigated to determine which lot is more robust. These parameters directly affect the functionality of the memory within a system and may determine thresholds necessary to mitigate failure.

Total Ionizing Dose (TID)↗

NASA NTRS2008

Performance of High Temperature Operational Amplifier, Type LM2904WH, under Extreme Temperatures

Operation of electronic parts and circuits under extreme temperatures is anticipated in NASA space exploration missions as well as terrestrial applications. Exposure of electronics to extreme temperatures and wide-range thermal swings greatly affects their performance via induced changes in the semiconductor material properties, packaging and interconnects, or due to incompatibility issues between interfaces that result from thermal expansion/contraction mismatch. Electronics that are designed to withstand operation and perform efficiently in extreme temperatures would mitigate risks for failure due to thermal stresses and, therefore, improve system reliability. In addition, they contribute to reducing system size and weight, simplifying its design, and reducing development cost through the elimination of otherwise required thermal control elements for proper ambient operation. A large DC voltage gain (100 dB) operational amplifier with a maximum junction temperature of 150 C was recently introduced by STMicroelectronics [1]. This LM2904WH chip comes in a plastic package and is designed specifically for automotive and industrial control systems. It operates from a single power supply over a wide range of voltages, and it consists of two independent, high gain, internally frequency compensated operational amplifiers. Table I shows some of the device manufacturer s specifications.

Patterson, Richard↗

NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Chen, Liang-Yu↗

NASA NTRS1999

K-Band Phased Array Developed for Low- Earth-Orbit Satellite Communications

Future rapid deployment of low- and medium-Earth-orbit satellite constellations that will offer various narrow- to wide-band wireless communications services will require phased-array antennas that feature wide-angle and superagile electronic steering of one or more antenna beams. Antennas, which employ monolithic microwave integrated circuits (MMIC), are perfectly suited for this application. Under a cooperative agreement, an MMIC-based, K-band phased-array antenna is being developed with 50/50 cost sharing by the NASA Lewis Research Center and Raytheon Systems Company. The transmitting array, which will operate at 19 gigahertz (GHz), is a state-of-the-art design that features dual, independent, electronically steerable beam operation ( 42 ), a stand-alone thermal management, and a high-density tile architecture. This array can transmit 622 megabits per second (Mbps) in each beam from Earth orbit to small Earth terminals. The weight of the total array package is expected to be less than 8 lb. The tile integration technology (flip chip MMIC tile) chosen for this project represents a major advancement in phased-array engineering and holds much promise for reducing manufacturing costs.

Anzic, Godfrey↗

NASA NTRS2004

Multisensor Arrays for Greater Reliability and Accuracy

Arrays of multiple, nominally identical sensors with sensor-output-processing electronic hardware and software are being developed in order to obtain accuracy, reliability, and lifetime greater than those of single sensors. The conceptual basis of this development lies in the statistical behavior of multiple sensors and a multisensor-array (MSA) algorithm that exploits that behavior. In addition, advances in microelectromechanical systems (MEMS) and integrated circuits are exploited. A typical sensor unit according to this concept includes multiple MEMS sensors and sensor-readout circuitry fabricated together on a single chip and packaged compactly with a microprocessor that performs several functions, including execution of the MSA algorithm. In the MSA algorithm, the readings from all the sensors in an array at a given instant of time are compared and the reliability of each sensor is quantified. This comparison of readings and quantification of reliabilities involves the calculation of the ratio between every sensor reading and every other sensor reading, plus calculation of the sum of all such ratios. Then one output reading for the given instant of time is computed as a weighted average of the readings of all the sensors. In this computation, the weight for each sensor is the aforementioned value used to quantify its reliability. In an optional variant of the MSA algorithm that can be implemented easily, a running sum of the reliability value for each sensor at previous time steps as well as at the present time step is used as the weight of the sensor in calculating the weighted average at the present time step. In this variant, the weight of a sensor that continually fails gradually decreases, so that eventually, its influence over the output reading becomes minimal: In effect, the sensor system "learns" which sensors to trust and which not to trust. The MSA algorithm incorporates a criterion for deciding whether there remain enough sensor readings that approximate each other sufficiently closely to constitute a majority for the purpose of quantifying reliability. This criterion is, simply, that if there do not exist at least three sensors having weights greater than a prescribed minimum acceptable value, then the array as a whole is deemed to have failed.

Immer, Christopher↗

NASA NTRS2002

Commercial-Off-The-Shelf Microelectromechanical Systems (MEMS) Flow-Measurement Probes Fabricated And Assembled

As an alternative to conventional tubing instrumentation for measuring airflow, designers and technicians at the NASA Glenn Research Center have been fabricating packaging components and assembling a set of unique probes using commercial-off-the-shelf microelectromechanical systems (MEMS) integrated circuits (computer chips). Using MEMS as an alternative has some compelling advantages over standard measurement devices. Sensor technologies have matured through high-production usage in industries such as automotive and aircraft manufacturers. Currently, MEMS are the choice in applications such as tire pressure monitors, altimeters, pneumatic controls, cable leak detectors, and consumer appliances. Conventional instrumentation uses tubing buried in the model aerodynamic surfaces or wind tunnel walls. The measurements are made when pressure is introduced at the tube opening. The pressure then must travel the tubing for lengths ranging from 20 to hundreds of feet before reaching an electronic signal conditioner. This condition causes a considerable amount of damping and requires measurements to be made only after the test rig has reached steady-state operation. The electronic MEMS pressure sensor is able to take readings continuously under dynamic states in nearly real time. The use of stainless steel tubing for pressure measurements requires many tubes to be cleaned, cut to length, carefully installed, and delicately deburred and spliced for use. A cluster of a few hundred 1/16-in.- (0.0625-in.-) diameter tubes (not uncommon in research testing facilities) can be several inches in diameter and may weigh enough to require two men to handle. Replacing hard tubing with electronic chips can eliminate much of the bulk. Each sensor would fit on the tip of the 1/16-in. tubing with room to spare. The P592 piezoresistive silicon pressure sensor (Lucas NovaSensor, Fremont, CA) was chosen for this project because of its cost, availability, and tolerance to extreme ambient conditions. The chip is 1 mm square by 0.6 mm thick (0.039 by 0.023 in.) with 0.12-mm (0.005-in.) wire connection tabs. Three MEMS chips were used to build the first type of flow-angularity probe. This MEMS probe will be demonstrated as an alternative to a standard tube type "Cobra Probe" now used routinely in wind tunnel and aeronautical hardware applications. The response time and accuracy would allow the probe to be translated on an actuator across a flow field, yielding precision dynamic measurements not possible with conventional instrumentation. The low profile, the minimal power requirement, the rugged construction, and the moderate cost all contribute to making MEMS sensors the enticing choice instrument in future research measurement needs. The MEMS probe efforts are a continuation of work initiated by Brian Willis, without whose foresight and efforts this project would never have been realized. This task was funded through cooperation with the NASA Electronic Parts and Packaging (NEPP) program at the Jet Propulsion Laboratory.

Redding, Chip↗

DOE OSTI2025

Thermal Management for Planar Package Power Electronics (CRADA Final Report)

The National Renewable Energy Laboratory (NREL) and John Deere Electronic Solutions (JDES) collaborated to develop and evaluate computer models and simulations related to the thermal performance of semiconductor device packaging for an inverter of an off-road vehicle ("Semiconductor Packaging"). The objective of the research was for NREL and JDES to develop a two or three-dimensional computer-aided design model of the Semiconductor Packaging ("Computer Model") for thermal performance evaluation in a simulation. The project developed computer models of a Semiconductor Package of silicon-carbide semiconductor devices with appropriate thermal dissipation via one or more of the following thermal features: a double-sided planar cooling configuration, an air-cooled configuration, a liquid-cooled configuration for off-road inverter applications in a relevant simulated operating environment. It is noted that surface area and prototype product embodiment consisting of air-cooled and liquid-cooled configurations may and may not be in direct contact with power semiconductor chips. The idea was to explore and develop packaging and thermal management technology for power semiconductors that was most effective in the performance yet had least burden in overall product cost for a given application.

33 ADVANCED PROPULSION SYSTEMS↗

NASA NTRS1998

MEMS Applications in Aerodynamic Measurement Technology

Microelectromechanical systems (MEMS) embodies the integration of sensors, actuators, and electronics on a single substrate using integrated circuit fabrication techniques and compatible bulk and surface micromachining processes. Silicon and its derivatives form the material base for the MEMS technology. MEMS devices, including microsensors and microactuators, are attractive because they can be made small (characteristic dimension about 100 microns), be produced in large numbers with uniform performance, include electronics for high performance and sophisticated functionality, and be inexpensive. For aerodynamic measurements, it is preferred that sensors be small so as to approximate measurement at a point, and in fact, MEMS pressure sensors, wall shear-stress sensors, heat flux sensors and micromachined hot wires are nearing application. For the envisioned application to wind tunnel models, MEMS sensors can be placed on the surface or in very shallow grooves. MEMS devices have often been fabricated on stiff, flat silicon substrates, about 0.5 mm thick, and therefore were not easily mounted on curved surfaces. However, flexible substrates are now available and heat-flux sensor arrays have been wrapped around a curved turbine blade. Electrical leads can also be built into the flexible substrate. Thus MEMS instrumented wind tunnel models do not require deep spanwise grooves for tubes and leads that compromise the strength of conventionally instrumented models. With MEMS, even the electrical leads can potentially be eliminated if telemetry of the signals to an appropriate receiver can be implemented. While semiconductor silicon is well known for its electronic properties, it is also an excellent mechanical material for MEMS applications. However, silicon electronics are limited to operations below about 200 C, and silicon's mechanical properties start to diminish above 400 C. In recent years, silicon carbide (SiC) has emerged as the leading material candidate for applications in high temperature environments and can be used for high-temperature MEMS applications. With SiC, diodes and more complex electronics have been shown to operate to about 600 C, while the mechanical properties of SiC are maintained to much higher temperatures. Even when MEMS devices show benefits in the laboratory, there are many packaging challenges for any aeronautics application. Incorporating MEMS into these applications requires new approaches to packaging that goes beyond traditional integrated circuit (IC) packaging technologies. MEMS must interact mechanically, as well as electrically with their environment, making most traditional chip packaging and mounting techniques inadequate. Wind tunnels operate over wide temperature ranges in an environment that is far from being a 'clean-room.' In flight, aircraft are exposed to natural elements (e.g. rain, sun, ice, insects and dirt) and operational interferences(e.g. cleaning and deicing fluids, and maintenance crews). In propulsion systems applications, MEMS devices will have to operate in environments containing gases with very high temperatures, abrasive particles and combustion products. Hence deployment and packaging that maintains the integrity of the MEMS system is crucial. This paper presents an overview of MEMS fabrication and materials, descriptions of available sensors with more details on those being developed in our laboratories, and a discussion of sensor deployment options for wind tunnel and flight applications.

Reshotko, E.↗

NASA NTRS2010

NASA Electronic Parts and Packaging (NEPP) Program - Update

This slide presentation reviews the goals and mission of the NASA Electronic Parts and Packaging (NEPP) Program. The NEPP mission is to provide guidance to NASA for the selection and application of microelectronics technologies, to improve understanding of the risks related to the use of these technologies in the space environment and to ensure that appropriate research is performed to meet NASA mission assurance needs. The program has been supporting NASA for over 20 years. The focus is on the reliability aspects of electronic devices. In this work the program also supports the electronics industry. There are several areas that the program is involved in: Memories, systems on a chip (SOCs), data conversion devices, power MOSFETS, power converters, scaled CMOS, capacitors, linear devices, fiber optics, and other electronics such as sensors, cryogenic and SiGe that are used in space systems. Each of these area are reviewed with the work that is being done in reliability and effects of radiation on these technologies.

LaBel, Kenneth A.↗

NASA NTRS2015

High Frequency Design Considerations for the Large Detector Number and Small Form Factor Dual Electron Spectrometer of the Fast Plasma Investigation on NASA's Magnetospheric Multiscale Mission

Each half of the Dual Electron Spectrometer (DES) of the Fast Plasma Investigation (FPI) on NASA's Magnetospheric MultiScale (MMS) mission utilizes a microchannel plate Chevron stack feeding 16 separate detection channels each with a dedicated anode and amplifier/discriminator chip. The desire to detect events on a single channel with a temporal spacing of 100 ns and a fixed dead-time drove our decision to use an amplifier/discriminator with a very fast (GHz class) front end. Since the inherent frequency response of each pulse in the output of the DES microchannel plate system also has frequency components above a GHz, this produced a number of design constraints not normally expected in electronic systems operating at peak speeds of 10 MHz. Additional constraints are imposed by the geometry of the instrument requiring all 16 channels along with each anode and amplifier/discriminator to be packaged in a relatively small space. We developed an electrical model for board level interactions between the detector channels to allow us to design a board topology which gave us the best detection sensitivity and lowest channel to channel crosstalk. The amplifier/discriminator output was designed to prevent the outputs from one channel from producing triggers on the inputs of other channels. A number of Radio Frequency design techniques were then applied to prevent signals from other subsystems (e.g. the high voltage power supply, command and data handling board, and Ultraviolet stimulation for the MCP) from generating false events. These techniques enabled us to operate the board at its highest sensitivity when operated in isolation and at very high sensitivity when placed into the overall system.

Microchannel plates high frequency performance↗

NASA NTRS2016

Evaluation of 10V Chip Polymer Tantalum Capacitors for Space Applications

Due to low ESR and safe failure mode, new technology chip polymer tantalum capacitors (CPTC) have gained popularity in the electronics design community, first in commercial applications, and now in hi-rel and space systems. The major drawbacks of these parts are high leakage currents, degradation under environmental stresses, and a relatively narrow temperature range of operating and storage conditions. Several studies have shown that a certain amount of moisture in polymer cathodes is necessary for a normal operation of the parts. This might limit applications of CPTCs in space systems and requires analysis of long-term exposure to deep vacuum conditions on their performance and reliability. High leakage currents and limited maximum operational temperature complicate accelerated testing that is necessary to assess long-term reliability and require new screening and qualification procedures for quality assurance. A better understanding of behavior of CPTCs as compared to traditional, MnO2, capacitors is necessary to develop adequate approaches for QA system for space applications. A specific of CPTCs is that different materials and processes might be used for low-voltage (10 V and less) and high-voltage (above 10 V) capacitors, so performance and degradation processes in these groups require separate analysis. In this work, that is a part of the NASA Electronic Parts and Packaging (NEPP) program, degradation of AC and DC characteristics under environmental stresses at different temperatures and voltages have been studied in nine lots of commercial and automotive grade capacitors rated to 10 V. Results of analysis of leakage currents, high temperature storage (HTS) up to 5000 hrs in vacuum and air at different temperatures, and Highly Accelerated Life Testing (HALT) in the range from 85 C to 145 C are presented. Temperature and voltage acceleration factors were calculated based on approximation of distributions of degradation rates with a general log-linear Weibull model. Mechanisms of degradation and failures, and requirements for screening and qualification testing are discussed.

Tantalum Capacitors↗

NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗

NASA NTRS2018

Standardizing GPU Radiation Test Approaches

While some Graphical Processing Units (GPUs) are discrete components (i.e.GTX1050), others take the form of an IP block or embedded engine within a System on Chip (SoC) device such as the Qualcomm Snapdragon"TM" 820 which contains a Qualcomm Adreno"TM" 530 GPU. Within this device are various functional blocks which can be exercised with software payloads. NVidia's Jetson"TM" TX1 SoC is provided on a System on Module (SOM). Within it are Central Processing Unit (CPU) cores and an nVidia GPU which can be accessed similarly to a discrete GPU coprocessor. While the packaging is different, each one of these GPUs needs to be tested using the same standardized code.

Single Event Effects (SEE)↗