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DOE OSTI2026

A Survey on the Expanding Scope and Interdisciplinary Opportunities for Processing-in-Memory Techniques

Processing-in-Memory (PIM) is emerging as a practical path to overcome the limitations of traditional von Neumann architectures. At its core, PIM systems implement computing primitives such as logic operations and multiply-accumulate acceleration through compute-in-memory, near-memory processing, or hybrid designs. The role of memory cells varies widely across technologies, acting as inputs, outputs, or analog accumulators through bit-lines and sense amplifiers. This diversity creates trade-offs in precision, bandwidth, latency, and programmability, making it difficult to build a unified understanding on the progress of the field. In this survey, we organize recent advances of PIM into three areas. First, we discuss the progress on the architectural optimizations of PIM and its integration with both DRAM and emerging non-volatile memories. Second, we examine how PIM is being used to accelerate key computing domains, including generative AI workloads and high-performance kernels, along with new approaches. Third, we highlight the growing adoption of PIM in computational sciences, where it is being applied to solve interdisciplinary problems such as genome analysis, mRNA quantification, mass spectrometry, quantum circuit simulation, wave modeling, and secure computation. Finally, we synthesize the major challenges that continue to slow PIM adoption, including manufacturing constraints, power delivery, thermal reliability, data consistency, runtime and memory-management coordination, and the difficulty of building portable software abstractions without sacrificing commercial viability. This work provides an updated, structured perspective on PIM’s potential across computing and computational sciences and the barriers that must be solved for it to reach its full impact.

Asifuzzaman, Kazi [Oak Ridge National Laboratory (↗

DOE OSTI2024

To have value, comparisons of high-throughput phenotyping methods need statistical tests of bias and variance

The gap between genomics and phenomics is narrowing. The rate at which it is narrowing, however, is being slowed by improper statistical comparison of methods. Quantification using Pearson’s correlation coefficient ( r ) is commonly used to assess method quality, but it is an often misleading statistic for this purpose as it is unable to provide information about the relative quality of two methods. Using r can both erroneously discount methods that are inherently more precise and validate methods that are less accurate. These errors occur because of logical flaws inherent in the use of r when comparing methods, not as a problem of limited sample size or the unavoidable possibility of a type I error. A popular alternative to using r is to measure the limits of agreement (LOA). However both r and LOA fail to identify which instrument is more or less variable than the other and can lead to incorrect conclusions about method quality. An alternative approach, comparing variances of methods, requires repeated measurements of the same subject, but avoids incorrect conclusions. Variance comparison is arguably the most important component of method validation and, thus, when repeated measurements are possible, variance comparison provides considerable value to these studies. Statistical tests to compare variances presented here are well established, easy to interpret and ubiquitously available. The widespread use of r has potentially led to numerous incorrect conclusions about method quality, hampering development, and the approach described here would be useful to advance high throughput phenotyping methods but can also extend into any branch of science. The adoption of the statistical techniques outlined in this paper will help speed the adoption of new high throughput phenotyping techniques by indicating when one should reject a new method, outright replace an old method or conditionally use a new method.

59 BASIC BIOLOGICAL SCIENCES↗

DOE OSTI2023

Gaseous fuel engine and operating strategy for limiting preignition in prechamber sparkplug

Operating a gaseous fuel engine system includes spark-igniting a gaseous hydrogen fuel and air in a prechamber sparkplug to ignite a main charge containing gaseous hydrogen fuel and air in a cylinder. Operating the gaseous fuel engine system also includes determining a preignition condition and conveying cooling air to the prechamber sparkplug based on the preignition condition to limit preignition of gaseous hydrogen fuel and air in the prechamber sparkplug. Related apparatus and control logic is also disclosed.

Singh, Jaswinder↗

DOE OSTI2025

Reassessment of Dose Contributions from the M-Area Glass Special Waste Form Buried in the E-Area Low-Level Waste Facility

During a recent revision to the groundwater (GW) and inadvertent human intruder (IHI) screening analysis report (Aleman and Hamm, 2023), weaknesses within the screening logic were observed resulting in U-235 being brought back into the list of radionuclides requiring inventory limits within the M-Area Glass SWF. In addition, while reviewing the earlier vadose zone (VZ) transport analysis efforts, an input deck error was observed in the U-234G VZ transport simulation.

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗

DOE OSTI2023

Better Than Worst-Case Decoding for Quantum Error Correction

The overheads of classical decoding for quantum error correction in cryogenic quantum systems grow rapidly with the number of logical qubits and their correction code distance. Decoding at room temperature is bottlenecked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget. To overcome these overheads, we are motivated by the observation that in the common case (over 90% of the time), error correction 'syndromes' are fairly trivial with high redundancy / sparsity, since the error correction codes are over-provisioned to be able to correct for uncommon worst-case complex scenarios (to ensure substantially low logical error rates). If suitably exploited, these trivial scenarios can be handled with insignificant overhead, thereby alleviating any bottlenecks towards handling the worst-case scenarios by state-of-the-art means. Here, we propose Better Than Worst-Case Decoding for Quantum Error Correction, targeting cryogenic quantum systems and Surface Code, consisting of: On-chip Clique Decoder: An extremely lightweight decoder for correcting trivial common-case errors, designed for the cryogenic domain. The decoder is implemented and evaluated for SFQ logic. Statistical Off-chip Bandwidth Allocation: A statistical confidence-based technique for allocation of off-chip decoding bandwidth, to efficiently handle the rare complex decodes that are not covered by the Clique Decoder. Decode-Overflow Execution Stalling: A method to stall circuit execution, for the worst-case scenarios in which the provisioned off-chip bandwidth is insufficient to complete all requested off-chip decodes. In all, BTWC decoding achieves 70-99+% off-chip bandwidth elimination across a range of logical and physical error rates, without significantly sacrificing the accuracy of a state-of-the-art off-chip decoder. Further, it achieves 10-1000x bandwidth reduction over prior bandwidth reduction techniques, as well as 15-37x resource overhead reduction compared to prior on-chip decoding.

cryogenic optimization↗

DOE OSTI2022

Adaptive Protective Relay Settings – A Vision to the Future

Adaptive relaying utilizes the continuously changing status of the power system as the basis for online adjustment of the power system relay settings. Fundamentally they are protection schemes that adjust settings and/or logic of operations based on the prevailing conditions of the system. These adjustments can include, but are not limited to, the logging of data for post-mortem analysis, communication throughout the system, as well as changing relay parameters. Adaptive relaying considers the fact that the status of a power system can change. These include system configuration changes, load effect, cold load pickup, end-of-line protection, transformer protection, and automatic reclosing. In this research, the author focus on the need for a secure, selective, and reliable system for adaptive overcurrent protection in T&D and Distributed Energy Systems. Various types of adaptive methods are presented and explained along with some pros and cons of each.

Mukherjee, Srijib↗

DOE OSTI2024

A nanoscale photonic thermal transistor for sub-second heat flow switching

Abstract Control of heat flow is critical for thermal logic devices and thermal management and has been explored theoretically. However, experimental progress on active control of heat flow has been limited. Here, we describe a nanoscale radiative thermal transistor that comprises of a hot source and a cold drain (both are ~250 nm-thick silicon nitride membranes), which are analogous to the source and drain electrodes of a transistor. The source and drain are in close proximity to a vanadium oxide (VO x )-based planar gate electrode, whose dielectric properties can be adjusted by changing its temperature. We demonstrate that when the gate is located close ( < ~1 µm) to the source-drain device and undergoes a metal-insulator transition, the radiative heat transfer between the source and drain can be changed by a factor of three. More importantly, our nanomembrane-based thermal transistor features fast switching times ( ~ 500 ms as opposed to minutes for past three-terminal thermal transistors) due to its small thermal mass. Our experiments are supported by detailed calculations that highlight the mechanism of thermal modulation. We anticipate that the advances reported here will open new opportunities for designing thermal circuits or thermal logic devices for advanced thermal management.

42 ENGINEERING↗

DOE OSTI2021

Method and apparatus for virtualizing the micro-op cache

Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions. When the control logic determines that micro-operations for one or more fetched instructions are stored in either the micro-operation cache or the conventional cache subsystem, the control logic causes the decode unit to transition to a reduced-power state.

Kalamatianos, John↗

DOE OSTI2023

Method and apparatus for virtualizing the micro-op cache

Kalamatianos, John↗

DOE OSTI2025

Reassessment of Dose Contributions from the Paducah Cask Special Waste Form Buried in the E-Area Low-Level Waste Facility

During a recent revision to the groundwater and inadvertent human intruder screening analysis report (Aleman and Hamm, 2023), weaknesses within the screening logic were observed resulting in the addition of U-235 being brought back into the list of radionuclides requiring inventory limits within the Paducah Cask special waste form (SWF). In addition, while reviewing the earlier vadose zone transport analysis efforts, an inconsistency was observed in the initial U-235P inventory that was supplied to the Consolidated Waste Tracking System (CWTS) back in 2009.

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗

DOE OSTI2020

Virtualized Logical Qubits: A 2.5D Architecture for Error-Corrected Quantum Computing

Current, near-term quantum devices have shown great progress in the last several years culminating recently with a demonstration of quantum supremacy. In the medium-term, however, quantum machines will need to transition to greater reliability through error correction, likely through promising techniques like surface codes which are well suited for near-term devices with limited qubit connectivity. We discover quantum memory, particularly resonant cavities with transmon qubits arranged in a 2.5D architecture, can efficiently implement surface codes with substantial hardware savings and performance/fidelity gains. Specifically, we virtualize logical qubits by storing them in layers of qubit memories connected to each transmon. Surprisingly, distributing each logical qubit across many memories has a minimal impact on fault tolerance and results in substantially more efficient operations. Our design permits fast transversal application of CNOT operations between logical qubits sharing the same physical address (same set of cavities) which are 6x faster than standard lattice surgery CNOTs. We develop a novel embedding which saves approximately 10x in transmons with another 2x savings from an additional optimization for compactness. Although qubit virtualization pays a 10x penalty in serialization, advantages in the transversal CNOT and in area efficiency result in fault-tolerance and performance comparable to conventional 2D transmon-only architectures. Our simulations show our system can achieve fault tolerance comparable to conventional two-dimensional grids while saving substantial hardware. Furthermore, our architecture can produce magic states at 1.22x the baseline rate given a fixed number of transmon qubits. Here, this is a critical benchmark for future fault-tolerant quantum computers as magic states are essential and machines will spend the majority of their resources continuously producing them. This architecture substantially reduces the hardware requirements for fault-tolerant quantum computing and puts within reach a proof-of-concept experimental demonstration of around 10 logical qubits, requiring only 11 transmons and 9 attached cavities in total.

quantum computing↗

DOE OSTI2025

AUTOMATIC GENERATION OF EVENT TREES AND FAULT TREES: A MODEL-BASED APPROACH

In the past few decades, increasing complexity in modern engineering systems has been driven by the integration of a large number of components and by the fact that the system operations involve many disciplines (e.g., thermal-hydraulics, plant operations, cyber-security). Current safety/reliability modeling approaches to such systems are labor intensive, difficult to learn, and rely heavily on simplistic Boolean logic to depict failure propagation and accident progression. While these methods serve well for simple systems (i.e., linear causal systems with limited small inter- and intra-system interactions), their results are difficult to verify when modeling complex systems (typically performed through the extensive use of modeling assumptions). The development of new methods is addressed to meet these challenges through a model-based system engineering (MBSE) lens. Under MBSE philosophy, every aspect of the system (form or function) is represented by a model that completely characterizes its architecture or behavior. MBSE approach greatly improves the management of design, analysis and verification of complex systems. An integration of Dynamic Probabilistic Risk Assessment (DPRA) methods with MBSE models is proposed to perform safety/reliability analyses of engineering systems. In particular, MBSE representation of the system (performed using Systems Modeling Language [SysML]) is coupled with DPRA methods to automatically generate event trees and fault trees.

97 - MATHEMATICS AND COMPUTING↗

DOE OSTI2023

Superconducting Hyperdimensional Associative Memory Circuit for Scalable Machine Learning

Here we propose a generalized architecture for the first rapid-single-flux-quantum (RSFQ) associative memory circuit. The circuit employs hyperdimensional computing (HDC), a machine learning (ML) paradigm utilizing vectors with dimensionality in the thousands to represent information. HDC designs have small memory footprints, simple computations, and simple training algorithms compared to superconducting neural network accelerators (SNNAs), making them a better option for scalable SFQ machine learning (ML) solutions. The proposed superconducting HDC (SHDC) circuit uses entirely on-chip RSFQ memory which is tightly integrated with logic, operates at 33.3 GHz, is applicable to general ML tasks, and is manufacturable at practically useful scales given current SFQ fabrication limits. Tailored to a language recognition task, SHDC consists of ~ 2-20 M Josephson junctions (JJs) and consumes up to three times less power than an analogous CMOS HDC circuit while achieving 78-84% higher throughput. SHDC is capable of outperforming the state of the art RSFQ SNNA, SuperNPU, by 48-99% for all benchmark NN architectures tested while occupying up to 90% less area and consuming up to nine times less power. To the best of the authors' knowledge, SHDC is currently the only superconducting ML approach feasible at practically useful scales for real-world ML tasks and capable of online learning.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2021

Logically Parallel Communication for Fast MPI+Threads Applications

Supercomputing applications are increasingly adopting the MPI+threads programming model over the traditional "MPI everywhere" approach to better handle the disproportionate increase in the number of cores compared with other on-node resources. In practice, however, most applications observe a slower performance with MPI+threads primarily because of poor communication performance. Recent research efforts on MPI libraries address this bottleneck by mapping logically parallel communication, that is, operations that are not subject to MPI's ordering constraints to the underlying network parallelism. Domain scientists, however, typically do not expose such communication independence information because the existing MPI-3.1 standard's semantics can be limiting. Researchers had initially proposed user-visible endpoints to combat this issue, but such a solution requires intrusive changes to the standard (new APIs). The upcoming MPI-4.0 standard, on the other hand, allows applications to relax unneeded semantics and provides them with many opportunities to express logical communication parallelism. Here in this article, we show how MPI+threads applications can achieve high performance with logically parallel communication. Through application case studies, we compare the capabilities of the new MPI-4.0 standard with those of the existing one and user-visible endpoints (upper bound). Logical communication parallelism can boost the overall performance of an application by over 2x.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Characterizing and Modeling the Influence of Geometry on the Performance of Superconducting Nanowire Cryotrons

The scaling of superconducting nanowire detectors to larger arrays is often limited by room-temperature-readout cabling. Cryogenic integrated circuits constructed from nanowire cryotrons, or nanocryotrons, can address this limitation by performing signal processing on chip. In this study, we characterize key performance metrics of the nanocryotron to elucidate its potential as a logical element in cryogenic integrated circuits and develop an electro-thermal model to connect material parameters with device performance. We find that the performance of the nanocryotron depends on the device geometry, and trade-offs are associated with optimizing the gain, jitter, and energy dissipation. Here, we demonstrate that nanocryotrons fabricated on niobium nitride can achieve a grey zone less than 210 nA wide for a 5 ns long input pulse corresponding to a maximum achievable gain of 48 dB, an energy dissipation of less than 20 aJ per operation, and a jitter of less than 60 ps.

Superconductor↗

DOE OSTI2020

Redox transistors based on TiO 2 for analogue neuromorphic computing

The ability to train deep neural networks on large data sets have made significant impacts onto artificial intelligence, but consume significant amounts of energy due to the need to move information from memory to logic units. In-memory "neuromorphic" computing presents an alternative framework that processes information directly on memory elements. In-memory computing has been limited by the poor performance of the analogue information storage element, often phase-change memory or memristors. To solve this problem, we developed two types of "redox transistors" using TiO 2 (anatase) which stores analogue information states through the electrochemical concentration of dopants in the crystal. The first type of redox transistor uses lithium as the electrochemical dopant ion, and its key advantage is low operating voltage. The second uses oxygen vacancies as the dopant, which is CMOS compatible and can retain state even when scaled to nanosized dimensions. Both devices offer significant advantages in terms of predictable analogue switching over conventional filamentary-based devices, and provide a significant advance in developing materials and devices for neuromorphic computing.

36 MATERIALS SCIENCE↗

DOE OSTI2021

A review of machine learning in building load prediction

The surge of machine learning in recent years has been empowering engineer modeling in various fields. The decreasing hardware cost, increasing data accessibility, and advances of building automation system (BAS) allow the collection and storage of a significant amount of building operation data. The two facts provide great opportunities of applying machine learning to building energy systems modeling and analysis. There are a great number of research papers on this topic but there lacks a comprehensive and general review to summarize the current development, limitations, gaps and future trend. In this review paper series, machine learning techniques in building energy system modeling and analysis are reviewed under the organization and logic of the machine learning definition by Tom M. Mitchell: a computer program is said to learn from experience E with respect to some class of tasks T and performance measure P if its performance at tasks in T, as measured by P, improves with experience E. This paper is the first part of the review paper series, which focuses on building load prediction. First, the applications of building load prediction model (task T) are reviewed. Then, the modeling algorithms improving machine learning performance and accuracy (performance P) are reviewed. At the same time, the literature on the data perspective for modeling (experience E), including data engineering from sensors level to data level, pre-processing, feature extraction and selection, is reviewed. Finally, what is well-studied and what is lacking but with great potential are concluded; the gaps between present and future utilization of machine learning techniques are identified; the future trend and development are also predicted. The target readers of this paper are not only researchers from the building side who can get exposed to cutting edge machine learning tools, but also those from machine learning side who can understand the potential and challenge to apply machine learning in buildings.

Liang, Zhang↗

DOE OSTI2024

Reinforcement learning pulses for transmon qubit entangling gates

The utility of a quantum computer is highly dependent on the ability to reliably perform accurate quantum logic operations. For finding optimal control solutions, it is of particular interest to explore model-free approaches, since their quality is not constrained by the limited accuracy of theoretical models for the quantum processor—in contrast to many established gate implementation strategies. In this work, we utilize a continuous control reinforcement learning algorithm to design entangling two-qubit gates for superconducting qubits; specifically, our agent constructs cross-resonance and CNOT gates without any prior information about the physical system. Using a simulated environment of fixed-frequency fixed-coupling transmon qubits, we demonstrate the capability to generate novel pulse sequences that outperform the standard cross-resonance gates in both fidelity and gate duration, while maintaining a comparable susceptibility to stochastic unitary noise. We further showcase an augmentation in training and input information that allows our agent to adapt its pulse design abilities to drifting hardware characteristics, importantly, with little to no additional optimization. Our results exhibit clearly the advantages of unbiased adaptive-feedback learning-based optimization methods for transmon gate design.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗