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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Performance of an X-γ ray detection system based on a thick silicon LGAD

We present the performance of a X-γ ray detection systems based on a 300 µm thick silicon low-gain avalanche diode (LGAD) and of an equivalent Diode structure without the gain layer, read-out by a custom-made low-noise charge amplifier. For the LGAD structure, the multiplication gains M s from 10.2 to 19.3 are measured, and the Equivalent Noise Charge (ENC) components have been studied in detail. As expected, a significant reduction of the white and 1/f voltage series and dielectric ENC components is observed with increasing gain, shortening the optimum peaking time to τ = 0.4÷8 μs depending on the gain value, with respect to the standard diode, while the parallel ENC component increases proportionally to the gain up to M s = 15. Setting the gain M s = 12.7, a minimum ENC = 34.5 electrons r.m.s. (298 eV FWHM) at τ = 1 μs is found. However, the electronic noise, evaluated on the pulser FWHM, is found to only marginally contribute to the width of the spectral lines of a radioactive source, which are dominated instead by the statistical noise of the charge multiplication within the LGAD structure. The spectral lines' excess width is found to be proportional to the signal multiplication gain M s and increases with the energy of the photons. A minimum line width of 850 eV FWHM at 13.9 keV is measured at room temperature, τ = 2 μs and a gain M s = 10.2.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Design and Characterization of a Burst Mode 20 Mfps Low Noise CMOS Image Sensor

This paper presents a novel ultra-high speed, high conversion-gain, low noise CMOS image sensor (CIS) based on charge-sweep transfer gates implemented in a standard 180 nm CIS process. Through the optimization of the photodiode geometry and the utilization of charge-sweep transfer gates, the proposed pixels achieve a charge transfer time of less than 10 ns without requiring any process modifications. Moreover, the gate structure significantly reduces the floating diffusion capacitance, resulting in an increased conversion gain of 183 µV/e−. This advancement enables the image sensor to achieve the lowest reported noise of 5.1 e− rms. To demonstrate the effectiveness of both optimizations, a proof-of-concept CMOS image sensor is designed, taped-out and characterized.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Measured gain suppression in FBK LGADs with different active thicknesses

In recent years, the gain suppression mechanism has been studied for large localized charge deposits in Low-Gain Avalanche Detectors (LGADs). LGADs are a thin silicon detector with a highly doped gain layer that provides moderate internal signal amplification. Using the CENPA Tandem accelerator at the University of Washington, the response of LGADs with different thicknesses to MeV-range energy deposits from a proton beam were studied. Three LGAD prototypes of 50 μm, 100 μm, and 150 μm were characterized. The devices' gain was determined as a function of bias voltage, incidence beam angle, and proton energy. This study was conducted in the scope of the PIONEER experiment, an experiment proposed at the Paul Scherrer Institute to perform high-precision measurements of rare pion decays. LGADs are considered for the active target (ATAR), and energy linearity is an important property for particle ID capabilities.

Particle tracking detectors↗
DOE OSTI2024

Radiation Hardened Engineered Substrates for Time and Space Resolution

Low Gain Avalanche Diodes (LGADs) have become sensors of choice for fast timing of minimum ionizing particles. The current generation of these devices suffer from only moderate radiation hardness, low fill factor, and limited design options. Cactus Materials Inc. proposes to develop sensors with gain layer implants buried beneath the surface which will, with AC coupling developed by Brookhaven National Laboratory (BNL) and University of California Santa Cruz (UC Santa Cruz) solve these problems. Fermilab has a major role in the CMS timing upgrade using the current generation of LGADs and development of AC-coupled, buried layer LGADs will solve some of the central problems inherent in this technology. Annex B included a two-year work plan, deliverables, schedule and funding for the project’s SBIR Phase II award to develop and test prototype LGADs utilizing wafer bonding technology and epitaxial growth, that will allow for fabrication of radiation hard AC coupled devices with 100% fill factor and adjustable operating point.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Advanced silicon tracking detector developments for the future Electron-Ion Collider

The proposed Electron-Ion Collider (EIC) will operate high-luminosity high-energy electron+proton and electron+nucleus collisions at the collision energies from 20 GeV to 141 GeV to solve several fundamental questions in the high energy and nuclear physics fields. Its instantaneous luminosity can reach 10 33-34 cm -2 s -1 and the bunching crossing rate is around 10 ns. The EIC project has received CD1 approval from the US DOE in 2021 and moves toward the machine design and preparation for construction. To realize various particle measurements with high precision at the future EIC, a low material-budget and high-granularity silicon vertex and tracking detector with fine spatial and momentum resolutions and nearly 4π solid angle coverage is desired. The Monolithic Active Pixel Sensor (MAPS) and AC Coupled Low Gain Avalanche Diode (AC-LGAD) technologies stand out of several advanced technology options for the EIC silicon vertex and tracking detector subsystems. The MAPS technology has advanced features of low material budget, low power consumption, good radiation resistance and fine spatial resolution. The AC-LGAD technology can achieve fast timing resolution. Latest studies and progress of the EIC silicon vertex and tracking detector conceptual design, performance validations in simulation and ongoing MAPS and AC-LGAD R&D will be shown. Furthermore, schedule and plan of the EIC project detector development will be discussed as well.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Performance of a Front End prototype ASIC for picosecond precision time measurements with LGAD sensors

For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region, to mitigate the effects of the increased pile-up. The chosen detection technology is Low Gain Avalanche Detector (LGAD) silicon sensors that can provide an excellent timing resolution below 50 ps. The front-end read-out ASIC must exploit the large signal derivative and small noise provided by the sensor, while keeping low power consumption. This paper presents the results on the first prototype of a front-end ASIC, named ALTIROC0, which contains the analog stages (preamplifier and discriminator) of the read-out chip. The ASIC was characterised both alone and as part of a module with a 2×2 LGAD array of 1.1×1.1 mm 2 pads bump-bonded to it. The various contributions of the electronics to the time resolution were investigated in test-bench measurements with a calibration setup. Both when the ASIC is alone or with a bump-bonded sensor, the jitter of the ASIC is better than 20 ps for an injected charge of 10 fC. The time walk effect, which arises from the different preamplifier response for various injected charges, can be corrected up to 10 ps using a Time Over Threshold measurement. The combined performance of the ASIC and the LGAD sensor, which was measured during a beam test campaign in October 2018 with pions of 120 GeV energy at the CERN SPS, is around 40 ps for all measured modules. All tested modules show good efficiency and time resolution uniformity.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade

We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity LHC upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 W for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the Time of Arrival (TOA) and the Time over Threshold (TOT) measurements without delay control. A double-strobe self-calibration scheme is used to compensate for process variation, temperature, and power supply voltage. The TDC is fabricated in a 65 nm CMOS technology. The overall performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps within its effective dynamic range of 11.6 ns. The effective measurement precision of the TOA is 5.6 ps and 9.9 ps with and without the nonlinearity correction, respectively. The TDC block consumes 97 W at the hit occupancy of 1%. Over a temperature range from 23 C to 78 C and a power supply voltage range from 1.05 V to 1.35 V (the nominal value of 1.20 V), the self-calibrated bin size of the TOA varies within 0.4%. The measured TDC performances meet the requirements except that more tests will be performed in the future to verify that the TDC complies with the radiation-tolerance specifications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

A sub-5 ps jitter time-to-digital converter ASIC with back-gate delay tuning in 22 nm CMOS

We present the design of a Time-to-Digital Converter (TDC) ASIC together with performance characterization results at cryogenic temperature (6-8 K), and at room temperature using emulated Low-Gain Avalanche Detector (LGAD) signals. The TDC design uses a two-step architecture with a ring-oscillator based counter and a Vernier delay line fine TDC. The TDC is implemented in an FD-SOI process, and back-gate tuning is used not only to correct threshold variation due to cryogenic operation, but also as a novel way to tune TDC delay elements with very little overhead. Using this technique, we demonstrate a design with very low power (0.5 mW) and area (0.003 mm 2 ). We present test results using the Fermilab Constant Fraction Discriminator (FCFD) ASIC to produce discriminated signals from an internal charge injection mechanism that mimics the waveform and signal amplitude of minimum ionizing particles impinging on LGAD sensors. We characterize the time precision of the full system and verify that the TDC ASIC contributes a negligible amount to the total system time precision, fully consistent with the expected jitter contribution of less than 5 ps. In conclusion, the results presented here demonstrate the utility of our TDC for applications in physics and quantum communications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16× 16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most probable value of around 15 fC. The discriminator generates the digital pulse, which provides the Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width) information. The prototype of ETROC (ETROC0) that implements a single channel of analog readout circuits has been evaluated with charge injection. The jitter of the analog readout circuits, measured from the discriminator's leading edge, is better than 16 ps for a charge larger than 15 fC with the sensor capacitance. The time walk resulting from different pulse heights can be corrected using the TOT measurement. The time resolution distribution has a standard deviation of 29 ps after the time-walk correction from the charge injection. At room temperature, the preamplifier's power consumption is measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode, respectively. Finally, the measured power consumption of the discriminator is 0.84 mW per pixel. With the ASIC alone or the LGAD sensor, The characterization performances fulfill the ETL's challenging requirements.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

The ETROC2 as the Final Version for CMS Endcap Timing Layer (ETL) Upgrade

The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD (Low Gain Avalanche Diodes) silicon devices, read out by ETROCs for precision timing measurement with down to ~30 ps timing resolution per track. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. The front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile. The ETROC chip is implemented in a commercial 65nm CMOS process. Each channel consists of a preamplifier, a discriminator, a TDC used for TOA (Time Of Arrival) and TOT (Time Over Threshold) measurements, and a memory for data storage and readout. An in-pixel auto threshold calibration is included, along with a self-testing pattern generator. The TOT is used for time-walk correction of the TOA measurement. The detailed hit information (TOA and TOT) from each cell will be read out from a local circular buffer after each Level-1 Accept (about 1 MHz). In addition, a charge injection circuit is implemented to allow for testing and calibration. For more detailed monitoring of the signal pulses, waveform sampling circuits are included for one pixel. The clock distribution is based on a 16x16 H-tree design with a shielding structure to alleviate potential interference. The global peripheral circuits include a PLL, a phase shifter, an I2C slave controller, a fast control block, a global readout, and a data driver along with an efuse and temperature sensor. The ETROC builds event data frames for each L1A selected event and is also capable of providing L1 trigger information for user-defined delayed hits. The main design challenge is how to extract precision timing information from the small LGAD signals in the presence of high irradiation fluence, while keeping the power consumption and digital activity low. The ETL design goal for the time resolution of 50 ps per hit is required to achieve a 35 ps arrival time measurement for a MIP particle, which has its track registered in two ETL disk layers. The LGAD contribution is known to be about 30 ps, this means that the jitter from the ETROC has to be kept below 40 ps. The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL and now becomes the final version. The ETROC2 chips have been extensively tested. We will present here new testing results including the bump bonding yield improvement study, the time walk correction (TWC) generality study with one pixel TWC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors, and readiness for the ETROC2 production for CMS ETL upgrade.

Liu, Tiehui [Fermilab] (ORCID:0009000765225605)↗
DOE OSTI2021

Resistive AC-Coupled Silicon Detectors: principles of operation and first results from a combined analysis of beam test and laser data

This paper presents the principles of operation of Resistive AC-Coupled Silicon Detectors (RSDs) and measurements of the temporal and spatial resolutions using a combined analysis of laser and beam test data. RSDs are a new type of n-in-p silicon sensor based on the Low-Gain Avalanche Diode (LGAD) technology, where the n+ implant has been designed to be resistive, and the read-out is obtained via AC-coupling. The truly innovative feature of RSD is that the signal generated by an impinging particle is shared isotropically among multiple read-out pads without the need for floating electrodes or an external magnetic field. Careful tuning of the coupling oxide thickness and the n+ doping profile is at the basis of the successful functioning of this device. Several RSD matrices with different pad width-pitch geometries have been extensively tested with a laser setup in the Laboratory for Innovative Silicon Sensors in Torino, while a smaller set of devices have been tested at the Fermilab Test Beam Facility with a 120 GeV/c proton beam. The measured spatial resolution ranges between 2.5μm for 70–100 pad-pitch geometry and 17μm with 200–500 matrices, a factor of 10 better than what is achievable in binary read-out (bin size/12). Beam test data show a temporal resolution of ~40ps for 200 μm pitch devices, in line with the best performances of LGAD sensors at the same gain.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Combined analysis of HPK 3.1 LGADs using a proton beam, beta source, and probe station towards establishing high volume quality control

The upgrades of the CMS and ATLAS experiments for the high luminosity phase of the Large Hadron Collider will employ precision timing detectors based on Low Gain Avalanche Detectors (LGADs). We present a suite of results combining measurements from the Fermilab Test Beam Facility, a beta source telescope, and a probe station, allowing full characterization of the HPK type 3.1 production of LGAD prototypes developed for these detectors. We demonstrate that the LGAD response to high energy test beam particles is accurately reproduced with a beta source. Finally, we further establish that probe station measurements of the gain implant accurately predict the particle response and operating parameters of each sensor, and conclude that the uniformity of the gain implant in this production is sufficient to produce full-sized sensors for the ATLAS and CMS timing detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Investigation of signal characteristics and charge sharing in AC-LGADs with laser and test beam measurements

AC-LGADs, also referred to as resistive silicon detectors, are a recent development of low-gain avalanche detectors (LGADs), based on a sensor design where the multiplication layer and n + contact are continuous, and only the metal layer is patterned. In AC-LGADs, the signal is capacitively coupled from the continuous, resistive n + layer over a dielectric to the metal electrodes. Therefore, the spatial resolution is not only influenced by the electrode pitch, but also the relative size of the metal electrodes. Signal propagation between the metallized areas and charge sharing between electrodes plays a larger role in these detectors than in conventional silicon sensors read out in DC mode. AC-LGADs from two manufacturers were studied in beam tests and with infrared laser scans. The impact of n + layer resistivity and metal electrode pitch on the charge sharing and achievable position resolution is shown. For strips with 100 μm pitch, a resolution of ¡ 5 μm can be reached. Additionally, the charge sharing between neighboring strips is investigated in more detail, indicating the induction of signal charge and subsequent re-sharing over the n + layer. Furthermore, an approach to identify signal sharing over large distances is presented.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Design and performance of the Fermilab Constant Fraction Discriminator ASIC

Here, we present the design and performance characterization results of the novel Fermilab Constant Fraction Discriminator ASIC (FCFD) developed to readout low gain avalanche detector (LGAD) signals by directly using a constant fraction discriminator (CFD) to measure signal arrival time. Silicon detectors with time resolutions less than 30ps will play a critical role in future collider experiments, and LGADs have been demonstrated to provide the required time resolution and radiation tolerance for many such applications. The FCFD has a specially designed discriminator that is robust against amplitude variations of the signal from the LGAD that normally requires an additional correction step when using a traditional leading edge discriminator. The application of the CFD directly in the ASIC promises to be more reliable and reduces the complication of evolving time-walk corrections throughout the operational lifetime of the detector system. We will present a summary of the measured performance of the FCFD for input signals generated by internal charge injection, LGAD signals from an infrared laser, and LGAD signals from minimum-ionizing particles. The mean time response for LGAD signals with charge ranging between 5 and 26 fC has been measured to vary no more than 10ps, orders of magnitude more stable than an uncorrected leading edge discriminator based measurement, and effectively removes the need for any additional time-walk correction. The measured contribution to the time resolution from the FCFD ASIC is found to be 10ps for signals with charge above 20fC.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Signal formation and sharing in AC-LGADs using the ALTIROC 0 front-end chip

The development of detectors that provide high resolution in four dimensions has attracted wide-spread interest in the scientific community for applications in high-energy physics, nuclear physics, medical imaging, mass spectroscopy as well as quantum information. However, finding a technology capable of fulfilling such aspiration proved to be an arduous task. Among other silicon-based candidates, the Low-Gain Avalanche Diode (LGAD) has already shown excellent timing performances but proved to be unsuitable for fine pixelization. Therefore, the AC-coupled LGAD (AC-LGAD) approach was introduced to provide high resolution in both time and space, making it a promising candidate for future 4D detectors. However, appropriate readout electronics must be developed to match the sensor's fast-time and fine-pitch capabilities. This is currently a major technological challenge. Here, we test AC-LGAD prototypes read out by the fast-time ASIC ALTIROC 0, originally developed for the readout of DC-coupled LGADs for the ATLAS experiment at the High Luminosity-LHC. Signal generated by either betas from a 90 Sr source or a focused infra-red laser were analyzed. This paper details the first successful readout of an AC-LGAD sensor using a readout chip. This result will pave the way for the design and construction of a new generation of AC-LGAD-based 4D detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade

We present the design and characterization of the first fullchain precision timing prototype ASIC, named ETL Readout Chipversion 1 (ETROC1) for the CMS MTD endcap timing layer (ETL)upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors todetect charged particles, with the goal to achieve a time resolutionof 40–50 ps per hit, and 30–40 ps per track with hits from twodetector layers. The ETROC1 is composed of a 5 × 5 pixelarray and peripheral circuits. The pixel array includes a4 × 4 active pixel array with an H-tree shaped networkdelivering clock and charge injection signals. Each active pixel iscomposed of various components, including a bump pad, a chargeinjection circuit, a pre-amplifier, a discriminator, adigital-to-analog converter, and a time-to-digital converter. Thesecomponents play essential roles as the front-end link in processingLGAD signals and measuring timing-related information. Theperipheral circuits provide clock signals and readoutfunctionalities. The size of the ETROC1 chip is7 mm× 9 mm. ETROC1 has been fabricated in a 65 nmCMOS process, and extensively tested under stimuli of chargeinjection, infrared laser, and proton beam. The time resolution ofbump-bonded ETROC1 + LGAD chipsets reaches 42–46 ps per hit in thebeam test.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

Studying AC-LGAD strip sensors from laser and testbeam measurements

Here, this paper presents the setup assembled to characterize and measure the spatial and timing resolutions of AC-coupled Low Gain Avalanche Diodes (AC-LGADs), using a 1060 nm laser source to deposit initial charges with a defined calibration methodology. The results were compared to those obtained with a 120 GeV proton beam. Despite the differences in the charge deposition mechanism between the laser and proton beam, the spatial and temporal resolutions were found to be compatible between the two sources after calibration. With 4D tracking detectors expected to play a vital role in upcoming collider experiments, we foresee this work as a way to evaluate the performance of semiconductor sensors that can augment testbeam measurements and accelerate R&D efforts. Additionally, simulation studies using Silvaco TCAD and Weightfield2 were carried out to understand the various contributing factors to the total time resolution in AC-LGAD sensors, measured using the laser source.

FOS: Physical sciences↗