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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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System is used for design, layout, and modification of large-scale-integrated (LSI) metal-oxide semiconductor (MOS) arrays. System is structured around small computer which provides real-time support for graphics storage display unit with keyboard, slave display unit, hard copy unit, and graphics tablet for designer/computer interface.
Computer uses custom-designed complementary metal-oxide semiconductor/silicon-on-sapphire LSI arrays with critical computer paths packages on thick-film hybrids.
Automatic Monitoring System for time-dependent dielectric breakdown tests ninety-nine metal-oxide semiconductor capacitors simultaneously. Each breakdown generates voltage spike registered on readouts and indicated by LED. Latching circuit prevents recording of possible subsequent breakdowns in same capacitor. In addition to research use, system could also be adapted for quality control.
Review is detailed compilation of safe handling practices for Metal-Oxide Semiconductor (MOS) circuit elements and other devices that are susceptible to damage by electrostatic discharge. Article lists safety procedures for all aspects of handling and use of these components. Included are guidelines for setting up static-free work station and list of materials and equipment needed to maintain antistatic protection. Appendix gives vendors of these items.
Low-temperature sinter of semiconductor and polymer resin is useful in manufacture of circuit boards, cables, and electroexplosive devices. Material can absorb large amounts of heat and can withstand repeated exposures to electrostatic discharges with little deteriorating effects. These characteristics offer significant advantages over high-temperature-sintered, metal-oxide semiconducting materials.
Device solves problem of differential voltage gain in sampled-data metal-oxide semiconductor, producing gain at any frequency compatible with CCD operation, with low noise, low power, good linearity, and high stability.
Adaptive active low-pass filters incorporate CMOS (Complimentary Metal-Oxide Semiconductor) analog switches (such as 4066 switch) that reduce variation in switch resistance when filter is switched to any selected transfer function.
Thermal fatigue and oxidation data were obtained for 11 plasma spray coated and 13 uncoated directionally solidified and single crystal MAR-M 246 blades. Blade coatings on the airfoil included several metal-oxide thermal barrier layers based on Al2O3, Cr2O3, or ZrO2. The 24 turbine blades were tested simultaneously for 3000 cycles in fluidized beds maintained at 950 and 25 C using a symmetrical 360 set thermal cycle. In 3000 cycles, only uncoated turbine blades exhibited cracking on the trailing edge near the platform; 3 of the 13 uncoated blades did not crack. Cracking occurred over the range 400 to 2750 cycles, with single crystal blades indicating the poorest thermal fatigue resistance. Oxidation of the uncoated blades was limited in 3000 cycles. All coatings indicated microscopically visible spalling at the trailing edge radius after 3000 cycles. Severe general spalling on the airfoil was observed for two multilayered coatings.
A new switching phenomenon in metal-oxide semiconductor tunnel junction has been discovered. With a sufficiently large negative bias applied to the electrode, incident visible light of intensity greater than about 1 microW/sq cm causes the reverse-biased junction to switch from a low-current to a high-current state. It is believed that hot-electron-induced impact ionization provides the positive feedback necessary for switching, and causes the junction to remain in its high-current state after the optical excitation is removed. The junction may be switched back to the low-current state electrically. The basic junction characteristics have been measured, and a simple model for the switching phenomenon has been developed.
Algorithm specifies sequence of input test signals and interpretation of resulting output signals for identifying stuck-open faults in complementary metal-oxide semiconductor (CMOS) integrated logic circuits. Incorporated in software for online production testing of CMOS circuits.
Sensitivity to ion beams is studied. Latchup effect subject of paper presenting results of testing 19 types of complementary metal-oxide semiconductor (CMOS) chips from six manufacturers. Report gives details of sensitivity of chips to latchup caused by argon and krypton ion beams. Identifies parasitic npnp paths and proides latchup cross section and qualitative explanation of latchup sensitivity for each chip type.
Pulse-width-modulated amplifier supplies high current as efficiently as low current needed for starting and running motor. Key to efficiency of motor-control amplifier is V-channel metal-oxide/semiconductor transistor Q1. Device has low saturation resistance. However, has large gate input capacitance and small margin between its turn-on voltage and maximum allowable gate-to-source voltage. Circuits for output stages overcome limitations of VMOS device.
The 800 C oxidation of oriented single crystals of Zr doped beta-NiAl was studied using transmission electron microscopy. The oxide phases and metal-oxide orientation relationships were determined to characterize the transient stages of oxidation prior to the transformation to or formation of alpha-Al2O3. On (001) and (012) metal orientations, NiAl2O4 was the first oxide to form followed by delta-Al2O3 which becomes the predominant oxide phase. All oxides were highly epitaxially related to the metal; the orientation relationships being function of parallel cation close-packed directions in the meta and oxide. On (011) and (111) metal orientations, gamma-Al2O3 became the predominant oxide phase rather than delta-Al2O3, indicating a structural stability from the highly epitaxial oxides. The relative concentration of aluminum in the oxide scales increased with time indicating preferential gamma-or delta-Al2O3 growth. The striking feature common to the orientation relationships is the alignment of 100 m and 110 ox directions, believed to result from the minimal 3 percent mismatch between the corresponding (100)m and (110)ox planes.
Techniques for satellite electromagnetic energy transfer and power conversion at millimeter and infrared wavelengths are discussed. The design requirements for rectenna receiving elements are reviewed for both coherent radiation sources and Earth thermal infrared emission. Potential power transmitters including gyrotrons, free electron lasers, and CO2 lasers are assessed along with the rectification properties of metal-oxide metal diode power converters.
Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.
Techniques appropriate to boards containing CMOS circuits detailed. Document presents procedure for applying thin conformal coating to such electronic assemblies as printed-circuit boards and wire-wrapped boards. Coating is from 1 to 7 mils (25 to 178 micrometers) thick and composed of room-temperature-vulcanizing (RTV) silicone. Specifies materials, equipment, spraying method, and quality requirements. Takes into account special needs of circuits made with complementary metal-oxide/semiconductor (CMOS) devices on circuit boards. Special attention given to preventing damage by electrostatic discharge, to which CMOS circuits especially sensitive.
Thin films of metal-oxide/polymer applied by ion-beam sputtering. Report describes experiments in development of coatings to protect polymers from bombardment by atomic oxygen.
Concept for determining susceptibility of integrated circuits to single-event upsets (SEU's) based on direct measurement of critical charge causing upset. Test circuit is modified version of standard complementary metal-oxide/semiconductor static cell. Contains six transistors, connected to form latch that retains state of cell set by input pulses. Makes possible to evaluate vulnerability to SEU during design and development of digital equipment.