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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1977

Concept report: Microprocessor control of electrical power system

An electrical power system which uses a microprocessor for systems control and monitoring is described. The microprocessor controlled system permits real time modification of system parameters for optimizing a system configuration, especially in the event of an anomaly. By reducing the components count, the assembling and testing of the unit is simplified, and reliability is increased. A resuable modular power conversion system capable of satisfying a large percentage of space applications requirements is examined along with the programmable power processor. The PC global controller which handles systems control and external communication is analyzed, and a software description is given. A systems application summary is also included.

Perry, E.↗
NASA NTRS1977

Microprocessor Seminar, phase 2

Workshop sessions and papers were devoted to various aspects of microprocessor and large scale integrated circuit technology. Presentations were made on advanced LSI developments for high reliability military and NASA applications. Microprocessor testing techniques were discussed, and test data were presented. High reliability procurement specifications were also discussed.

Scott, W. R.↗
NASA NTRS1977

Loran-C digital word generator for use with a KIM-1 microprocessor system

The problem of translating the time of occurrence of received Loran-C pulses into a time, referenced to a particular period of occurrence is addressed and applied to the design of a digital word generator for a Loran-C sensor processor package. The digital information from this word generator is processed in a KIM-1 microprocessor system which is based on the MOS 6502 CPU. This final system will consist of a complete time difference sensor processor for determining position information using Loran-C charts. The system consists of the KIM-1 microprocessor module, a 4K RAM memory board, a user interface, and the Loran-C word generator.

Nickum, J. D.↗
NASA NTRS1977

An application of microprocessors to a Mars Roving Vehicle

This paper presents an approach to a microprocessor based computing system for a Mars Roving Vehicle. This represents a practical example in that it combines a breadboard robot (the Rover) with a distributed microprocessor computing system, both of which are under development at JPL and are being considered for a 1984 Mars Rover Mission. A summary of the Rover functions is presented, along with an approach of applying distributed computers. The Rover is then partitioned into its main subsystems (executive, locomotion, manipulation, and vision) and subsystem and system interfaces established. Computing requirements are discussed and a system diagram developed.

Dobrotin, B. M.↗
NASA NTRS1979

Microprocessor-based interface for oceanography

Ocean floor imaging system incorporates five identical microprocessor-based interface units each assigned to specific sonar instrument to simplify system. Central control module based on same microprocessor eliminates need for custom tailoring hardware interfaces for each instrument.

Hansen, G. R.↗
NASA NTRS1978

A multi-microprocessor system for finite element structural analysis

During the last few years, advances in microprocessor technology have spurred a renewed interest in special-purpose computers. The microprocessor has become small, inexpensive, and powerful enough to be considered as a building block for special-purpose hardware. A description is presented of the architecture of a prototype 'finite element machine' currently being built. Attention is given to details regarding the finite element analysis problem, the arrangement of the processors as finite element nodes in the structural model, the influence of the architecture on the solution algorithm, interprocessor communication primitives, and the performance of the finite element machine.

Jordan, H. F.↗
NASA NTRS1978

Design of a microprocessor based packet switch

The design of a packet switch incorporating a minicomputer to control and process data packets in a communications system has been reported. This paper proposes a design which uses a 6500 series microprocessor to realize the functions of a message switch in order to evaluate the viability of microprocessors in this application. The proposed design realizes the functions of header analysis, packet security, error control and line prioritization. The system hardware and software are presented together with a brief description of operation.

Carville, D. E.↗
NASA NTRS1979

Application of a microprocessor controlled lidar to tropospheric ozone measurements

A microprocessor controlled lidar system under construction at the NASA Goddard Space Flight Center is described and the problems in making space-based measurements of tropospheric ozone are considered. The differential absorption lidar using a dual wavelength, pulsed CO2 laser and direct detection receiver can significantly improve the existing global data base on tropospheric ozone burden. Sensitivity to tropospheric ozone can be obtained in the spaceborne version of lidar by selecting laser lines located in the wings of the target zone lines. Simulation studies using various laser line pairs in the P-branch of the CO2 9.4 micron band show that the ozone burden retrieval may be weighted to particular altitude regions. These simulation studies are based on numerical integration of differences in absorption coefficient at the two selected laser wavelengths using the AFGL absorption line parameter compilations, U.S. Standard Atmosphere ozone profile, and laser software. Simulation, data collection and reduction are performed by a microprocessor subsystem of the CO2 lidar.

Stewart, R. W.↗
NASA NTRS1980

A microprocessor based high speed packet switch for satellite communications, executive summary

The feasibility of using microprocessors to control satellite-borne packet switching was investigated by designing a packet switch architecture suitable for microprocessor control, using 2900 series components to design the processor(s), and evaluating the packet switch in terms of system throughput, delay, and queue sizes without the packet switch. System architecture for one, three, and multiple processors was designed and evaluated. The production cost of the single processor packet switch is estimated at $500,000, excluding cost of development. The three processor version which can support a maximum throughput of 500,000 packets/sec is estimated to have a production cost of under $100,000. For the multiple processor system, cost is believed to be proportional to throughput, with $1,000,000 for 500,000 packets/sec being the proportionality factor.

Arozullah, M.↗
NASA NTRS1979

A microprocessor-based cardiotachometer

The development of a highly accurate and reliable cardiotachometer for measuring the heart rate of test subjects is discussed. It measures heart rate over the range of 30 to 250 beats/minute and gives instantaneous (beat to beat) updates on the system output so that occasional noise artifacts or ectopic beats could be more easily identified except that occasional missed beats caused by switching ECG leads should not cause a change in the output. The cardiotachometer uses an improved analog filter and R-wave detector and an Intel 8080A microprocessor to handle all of the logic and arithmetic necessary. By using the microprocessor, future hardware modifications could easily be made if functional changes were needed.

Donaldson, J. A.↗
NASA NTRS1980

A microprocessor based high speed space-borne packet switch

The design and performance evaluation of a single microprocessor based packet switch for use on-board a satellite are presented. The primary design criterion is to maximize the system throughput. A number of protocols and their impact on the switch design are discussed. Stem and processor hardware architectures are described. The flow charts of the software required to accomplish the essential functions are presented and modification needed for use in a multisatellite network are also indicated. Maximum throughput attainable is calculated, desirable characteristics of microprocessors for this application are pointed out. A queue theoretic model of the packet switch has been developed. Analytical relationships of the average waiting times and the queue sizes at the queues and the overall average response time with the various design parameters of the switch have been obtained. A number of graphs showing the effect of variation in the number of input and output lines, data rates, destination functions, speed of output lines and some other design parameters on the performance of the switch are presented and discussed.

Arozullah, M.↗
NASA NTRS1980

Digital multiplexing of analog data in a microprocessor controlled data acquisition system

The purpose of the paper is to explore the ramifications of doing the multiplexing function in the digital domain and of using the microprocessor to replace the hardwired control logic which resides in the typical analog to digital converter. Two types of conversion (one working in parallel inputs, and one in sequential order) strategies are discussed where the microprocessor is in full control of the conversion. One advantage of using a digital multiplexor is that, contrary to an analog multiplexor, it does not degrade the fidelity of the conversion process.

Cliff, R. A.↗
NASA NTRS1980

Microprocessor realizations of range and range-rate filters in radar systems

This paper describes the implementation of digital radar range-rate filters on a microprocessor-based system. A range-rate filter processes a digitized noisy range signal to recover smoothed range data and its derivative, range rate. Two filter designs are implemented. Considerations aiding their efficient operation on an 8-bit microprocessor are discussed. The filters are subjected to a noisy range input signal of known variance, and the associated output signals are statistically analysed to determine noise-rejection characteristics. These results are compared to analytical predictions.

Fleischer, D.↗
NASA NTRS1980

Microprocessors for real time displays and control of space teleoperators

This paper describes the use of microprocessors for smart displays in a space teleoperator project at the Jet Propulsion Laboratory. The application of microprocessor systems to demonstrate the utility of smart displays for a wrist mounted force/torque sensor and end-effector mounted proximity sensors are discussed as are the laboratory hardware and software configurations. These displays assist the operator in making critical real time decisions. Avenues for future development of these concepts are also presented.

Paine, G.↗
NASA NTRS1980

Application of a microprocessor to a spacecraft attitude control

The attitude control system (ACS) microprocessor development work spanned three main design areas: hardware and instruction set, ACS firmware, and hardware firmware verification testing. The processor hardware utilizes two parallel 4 bit microprocessors. The firmware includes data processing for five sensors, four attitude control laws, and telemetry and commands.

Brady, D. H.↗
NASA NTRS1979

A microprocessor based satellite borne packet switch

Design considerations applicable to a space-borne single microprocessor based packet switch are identified. These include system architecture decisions and microprocessor selection. The division of tasks among different subroutines is discussed. The primary design criterion is to maximize throughput. The extension to a multi-satellite network is discussed. The maximum throughput attainable is derived. A queue theoretic model has been developed and expressions for average response times and average queue sizes are obtained. A number of graphs showing the effect of various design parameters on the average response time and the average queue sizes are presented.

Crist, S. C.↗
NASA NTRS1982

Design approach for a microprocessor-based GPS time transfer receiver

The design concept and characteristics of a self-contained microprocessor-based Global Positioning System time transfer receiver is described. A prototype of this unit is currently in the test phase. It employs two-bit digital baseband correlation rather than analog IF correlation of the signals with the reference code. The correlator, numerically controlled oscillators and code generator are implemented in a special-purpose digital signal processor. The time is recovered in the digital code tracking loop, and final corrections are applied in the control processor. Other features of this design are: (1) drift-free digital mechanization; (2) high reliability of digital circuits; (3) flexible control capability of the microprocessor; and (4) potential for a high degree of digital VLSI chip development leading to compact, low-cost units.

Ould, P. C.↗