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NASA NTRS1986

Dry etching of beta-SiC in CF4 and CF4 + O2 mixtures

Dry etching of cubic (100) beta-SiC single-crystal thin films produced via chemical-vapor deposition (CVD) has been performed in CF4 and CF4 + O2 mixtures, in both the reactive-ion-etching (RIE) and plasma-etching modes. The latter process yielded measurable etch rates, but produced a dark surface layer which appears, from the results of secondary-ion mass spectrometry, to be residual SiC. The RIE samples had no residual layer, but Auger electron spectroscopy did reveal a C-rich surface. The optimal RIE conditions were obtained with 10 sccm of pure CF4 at 40 mtorr and a power density of 0.548 W/sq cm, giving an etch rate of 23.3 nm/min. Neither the increase of temperature between 293 and 573 K, nor the incremental addition of O2 to CF4 to 50 percent, produced any strong effect on the etch rates of SiC during RIE. Pictorial evidence of fine line structures produced by RIE of beta-SiC films are also presented.

Palmour, J. W.↗

NASA NTRS2004

Multi-Functional, Micro Electromechanical Silicon Carbide Accelerometer

A method of bulk manufacturing SiC sensors is disclosed and claimed. Materials other than SiC may be used as the substrate material. Sensors requiring that the SiC substrate be pierced are also disclosed and claimed. A process flow reversal is employed whereby the metallization is applied first before the recesses are etched into or through the wafer. Aluminum is deposited on the entire planar surface of the metallization. Photoresist is spun onto the substantially planar surface of the Aluminum which is subsequently masked (and developed and removed). Unwanted Aluminum is etched with aqueous TMAH and subsequently the metallization is dry etched. Photoresist is spun onto the still substantially planar surface of Aluminum and oxide and then masked (and developed and removed) leaving the unimidized photoresist behind. Next, ITO is applied over the still substantially planar surface of Aluminum, oxide and unimidized photoresist. Unimidized and exposed photoresist and ITO directly above it are removed with Acetone. Next, deep reactive ion etching attacks exposed oxide not protected by ITO. Finally, hot phosphoric acid removes the Al and ITO enabling wires to connect with the metallization. The back side of the SiS wafer may be also etched.

Robert S Okojie↗

NASA NTRS2004

Multi-functional micro electromechanical devices and method of bulk manufacturing same

Okojie, Robert S.↗

NASA NTRS2000

Fracture Tests of Etched Components Using a Focused Ion Beam Machine

Many optical MEMS device designs involve large arrays of thin (0.5 to 1 micron components subjected to high stresses due to cyclic loading. These devices are fabricated from a variety of materials, and the properties strongly depend on size and processing. Our objective is to develop standard and convenient test methods that can be used to measure the properties of large numbers of witness samples, for every device we build. In this work we explore a variety of fracture test configurations for 0.5 micron thick silicon nitride membranes machined using the Reactive Ion Etching (RIE) process. Testing was completed using an FEI 620 dual focused ion beam milling machine. Static loads were applied using a probe. and dynamic loads were applied through a piezo-electric stack mounted at the base of the probe. Results from the tests are presented and compared, and application for predicting fracture probability of large arrays of devices are considered.

Kuhn, Jonathan, L.↗

NASA NTRS2010

Fabrication and Modification of Nanoporous Silicon Particles

Silicon-based nanoporous particles as biodegradable drug carriers are advantageous in permeation, controlled release, and targeting. The use of biodegradable nanoporous silicon and silicon dioxide, with proper surface treatments, allows sustained drug release within the target site over a period of days, or even weeks, due to selective surface coating. A variety of surface treatment protocols are available for silicon-based particles to be stabilized, functionalized, or modified as required. Coated polyethylene glycol (PEG) chains showed the effective depression of both plasma protein adsorption and cell attachment to the modified surfaces, as well as the advantage of long circulating. Porous silicon particles are micromachined by lithography. Compared to the synthesis route of the nanomaterials, the advantages include: (1) the capability to make different shapes, not only spherical particles but also square, rectangular, or ellipse cross sections, etc.; (2) the capability for very precise dimension control; (3) the capacity for porosity and pore profile control; and (4) allowance of complex surface modification. The particle patterns as small as 60 nm can be fabricated using the state-of-the-art photolithography. The pores in silicon can be fabricated by exposing the silicon in an HF/ethanol solution and then subjecting the pores to an electrical current. The size and shape of the pores inside silicon can be adjusted by the doping of the silicon, electrical current application, the composition of the electrolyte solution, and etching time. The surface of the silicon particles can be modified by many means to provide targeted delivery and on-site permanence for extended release. Multiple active agents can be co-loaded into the particles. Because the surface modification of particles can be done on wafers before the mechanical release, asymmetrical surface modification is feasible. Starting from silicon wafers, a treatment, such as KOH dipping or reactive ion etching (RIE), may be applied to make the surface rough. This helps remove the nucleation layer. A protective layer is then deposited on the wafer. The protective layer, such as silicon nitride film or photoresist film, protects the wafer from electrochemical etching in an HF-based solution. A lithography technique is applied to pattern the particles onto the protective film. The undesired area of the protective film is removed, and the protective film on the back side of the wafer is also removed. Then the pattern is exposed to HF/surfactant solution, and a larger DC electrical current is applied to the wafers for a selected time. This step removes the nucleation layer. Then a DC current is applied to generate the nanopores. Next, a large electrical current is applied to generate a release layer. The particles are mechanically suspended in the solvent and collected by filtration or centrifuge.

Ferrari, Mauro↗

NASA NTRS2007

Design and Fabrication Highlights Enabling a 2 mm, 128 Element Bolometer Array for GISMO

The Backshort-Under-Grid (BUG) superconducting bolometer array architecture is intended to be highly versatile, operating in a large range of wavelengths and background conditions. We have undertaken a three-year program to develop key technologies and processes required to build kilopixel arrays. To validate the basic array design and to demonstrate its applicability for future kilopixel arrays, we have chosen to demonstrate a 128 element bolometer array optimized for 2 mm wavelength using a newly built Goddard instrument, GISMO (Goddard /RAM Superconducting 2-millimeter Observer). The arrays are fabricated using batch wafer processing developed and optimized for high pixel yield, low noise, and high uniformity. The molybdenum-gold superconducting transition edge sensors are fabricated using batch sputter deposition and are patterned using dry etch techniques developed at Goddard. With a detector pitch of 2 mm 8x16 array for GISMO occupies nearly one half of the processing area of a 100 mm silicon-on-insulator starting wafer. Two such arrays are produced from a single wafer along with witness samples for process characterization. To provide thermal isolation for the detector elements, at the end of the process over 90% of the silicon must be removed using deep reactive ion etching techniques. The electrical connections for each bolometer element are patterned on the top edge of the square grid supporting the array. The design considerations unique to GISMO, key fabrication challenges, and laboratory experimental results will be presented.

Allen, Christine↗

NASA NTRS2019

Fabrication of Phononic Filter Structures for Far-IR/sub-mm Detector Applications

A photon noise limited sub-mm/far-IR cold telescope in space will require detectors with noise equivalent power (NEP) less than 1x10-19W/Hz1/2for imaging applications and at least an order of magnitude lower for spectroscopic studies. The detector NEP can be reduced by lowering the operation temperature and improving the thermal isolation between the bolometer and a heat bath. We report on the fabrication of membrane isolated transition edge sensor bolometers incorporating compact (<50 μm) thermal isolation beams based on phononic filters. Phononic filters are created by etching quasi-periodic nanoscale structures into supporting thermo-mechanical beams. The cross-sectional dimensions of the etched features are less than the thermal wavelength at the operating temperature, enabling coherent phonon transport to take place in one dimension. The phonon stop-band can be tuned by adjusting the scale of the quasi-periodic structures. Cascading multiple filter stages can increase bandwidth and provide improved thermal isolation similar to the function of a multi-stage electrical filter. We describe the fabrication of AlMn based transition edge sensor bolometers on silicon and silicon nitride membranes isolated by one-and two-dimensional phononic filters. The phononic filters are patterned through electron beam lithography and isolated with deep reactive ion etching.

Phononic↗

NASA NTRS2005

In Situ Electrochemical Deposition of Microscopic Wires

A method of fabrication of wires having micron and submicron dimensions is built around electrochemical deposition of the wires in their final positions between electrodes in integrated circuits or other devices in which the wires are to be used. Heretofore, nanowires have been fabricated by a variety of techniques characterized by low degrees of controllability and low throughput rates, and it has been necessary to align and electrically connect the wires in their final positions by use of sophisticated equipment in expensive and tedious post-growth assembly processes. The present method is more economical, offers higher yields, enables control of wire widths, and eliminates the need for post-growth assembly. The wires fabricated by this method could be used as simple electrical conductors or as transducers in sensors. Depending upon electrodeposition conditions and the compositions of the electroplating solutions in specific applications, the wires could be made of metals, alloys, metal oxides, semiconductors, or electrically conductive polymers. In this method, one uses fabrication processes that are standard in the semiconductor industry. These include cleaning, dry etching, low-pressure chemical vapor deposition, lithography, dielectric deposition, electron-beam lithography, and metallization processes as well as the electrochemical deposition process used to form the wires. In a typical case of fabrication of a circuit that includes electrodes between which microscopic wires are to be formed on a silicon substrate, the fabrication processes follow a standard sequence until just before the fabrication of the microscopic wires. Then, by use of a thermal SiO-deposition technique, the electrodes and the substrate surface areas in the gaps between them are covered with SiO. Next, the SiO is electron-beam patterned, then reactive-ion etched to form channels having specified widths (typically about 1 m or less) that define the widths of the wires to be formed. Drops of an electroplating solution are placed on the substrate in the regions containing the channels thus formed, then the wires are electrodeposited from the solution onto the exposed portions of the electrodes and into the channels. The electrodeposition is a room-temperature, atmospheric-pressure process. The figure shows an example of palladium wires that were electrodeposited into 1-mm-wide channels between gold electrodes.

Yun, Minhee↗

NASA NTRS1984

Etching of diamond with argon and oxygen ion beams

The angular dependences of the sputter yield of (100) single crystal diamond under argon and oxygen ion beams were investigated. For argon ion beams a large increase in the sputter yield was observed as the angle of incidence was increased from the normal, with a maximum occurring at approximately 60 deg from the normal. The magnitude of the increase and the angle at which the maximum was observed were dependent on the ion energy and species. The shape of the yield versus angle of incidence curve indicated the presence of a highly damaged surface layer. Large deviations from this curve were observed where ion incidence was along channeling directions. Studies with oxygen ion beams showed almost no angular dependence for 500 eV ions while at an energy of 1000 eV the angular dependence was similar to that for argon ions. At normal incidence the yield for 500 eV oxygen ions was seven times larger than that for 500 eV argon ions. For 1000 eV oxygen and argon ions the corresponding ratio is only 2.5. Implications for mechanisms of inert and reactive ion etching are discussed. Application of the data to ion beam shaping of diamond tips for ultrahigh pressure research is discussed.

Whetten, T. J.↗

NASA NTRS1979

Industrial ion source technology

In reactive ion etching of Si, varying amounts of O2 were added to the CF4 background. The experimental results indicated an etch rate less than that for Ar up to an O2 partial pressure of about .00006 Torr. Above this O2 pressure, the etch rate with CF4 exceeded that with Ar alone. For comparison the random arrival rate of O2 was approximately equal to the ion arrival rate at a partial pressure of about .00002 Torr. There were also ion source and ion pressure gauge maintenance problems as a result of the use of CF4. Large scale (4 sq cm) texturing of Si was accomplished using both Cu and stainless steel seed. The most effective seeding method for this texturing was to surround the sample with large inclined planes. Designing, fabricating, and testing a 200 sq cm rectangular beam ion source was emphasized. The design current density was 6 mA/sq cm with 500 eV argon ions, although power supply limitations permitted operation to only 2 mA/sq cm. The use of multiple rectangular beam ion sources for continuous processing of wider areas than would be possible with a single source was also studied. In all cases investigated, the most uniform coverage was obtained with 0 to 2 cm beam overlay. The maximum departure from uniform processing at optimum beam overlap was found to be +15%.

Kaufman, H. R.↗

NASA NTRS1982

Holographic fabrication of gratings in metal substrates

A program for investigating the grain enlargement resulting from the laser recrystallization of a thin gallium arsenide film on a patterned substrate, a technique known as graphoepitaxy was evaluated. More specifically, the effects of recrystallizing an uncapped gallium arsenide film using a continuous wave neodymium YAG laser operating at 1.06 microns were studied. In an effort to minimize arsenic loss from the film, the specimens were held in an arsine atmosphere during recrystallization. Two methods for fabricating patterned substrates were developed, one using reactive ion etching of a molybdenum film on both sapphire and silicon substates and another by preferential wet etching of a silicon substrate onto which a film of molybdenum was subsequently deposited.

Fletcher, R. M.↗

NASA NTRS1983

Spindt cold cathode electron gun development program

A thin film field emission cathode array and an electron gun based on this emitter array are summarized. Fabricating state of the art cathodes for testing at NASA and NRL, advancing the fabrication technology, developing wedge shaped emitters, and performing emission tests are covered. An anistropic dry etching process (reactive ion beam etching) developed that leads to increasing the packing density of the emitter tips to about 5 x 10 to the 6th power/square cm. Tests with small arrays of emitter tips having about 10 tips has demonstrated current densities of over 100 A/sq cm. Several times using cathodes having a packing density of 1.25 x 10 to the 6th power tips/sq cm. Indications are that the higher packing density achievable with the dry etch process may extend this capability to the 500 A/sq cm range and beyond. The wedge emitter geometry was developed and shown to produce emission. This geometry can (in principle) extend the current density capability of the cathodes beyond the 500 A/sq cm level. An emission microscope was built and tested for use with the cathodes.

Spindt, C. A.↗

NASA NTRS1991

Silicon carbide, a semiconductor for space power electronics

After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the areas of crystal growth and device fabrication technology. High quality single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

Powell, J. Anthony↗

NASA NTRS1991

High-voltage 6H-SiC p-n junction diodes

A chemical vapor deposition (CVD) process has been used to produce device structures of n- and p-type 6H-SiC epitaxial layers on commercially produced single-crystal 6H-SiC wafers. Mesa-style p-n junction diodes were successfully fabricated from these device structures using reactive ion etching, oxide passivation, and electrical contact metallization techniques. When tested in air, the 6H-SiC diodes displayed excellent rectification characteristics up to the highest temperature tested, 600 C. To observe avalanche breakdown of the p-n junction diodes, testing under a high-electrical-strength liquid was necessary. The avalanche breakdown voltage was 1000 V representing the highest reverse breakdown voltage to be reported for any CVD-grown SiC diode.

Matus, L. G.↗

NASA NTRS1991

Silicon carbide, a semiconductor for space power electronics

After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the area of crystal growth and device fabrication technology. High quality of single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

Powell, J. A.↗

NASA NTRS1993

Fabrication of micro-optical devices

We have fabricated a variety of micro-optic components including Fresnel and non-Frensel lenses, off-axis and dispersive lenses with binary stepped contours, and analog contours. Process details for all lens designs fabricated are given including multistep photolithography for binary fabrication and grayscale mask photolithography for analog fabrication. Reactive ion etching and ion beam milling are described for the binary fabrication process, while ion beam milling was used for the analog fabrication process. Examples of micro-optic components fabricated in both Si and CdTe substrates are given.

Anderson, W. W.↗

NASA NTRS1996

AlGaN Channel Transistors for Power Management and Distribution

Contained within is the Final report of a Phase 1 SBIR program to develop AlGaN channel junction field effect transistors (JFET). The report summarizes our work to design, deposit, and fabricate JFETS using molecular beam epitaxy growth AlGaN. Nitride growth is described using a RF atomic nitrogen plasma source. Processing steps needed to fabricate the device such as ohmic source-drain contacts, reactive ion etching, gate formation, and air bride fabrication are documented. SEM photographs of fabricated power FETS are shown. Recommendations are made to continue the effort in a Phase 2 Program.

ENERGY MANAGEMENT↗

NASA NTRS1998

160-190 GHz Monolithic Low Noise Amplifiers

This paper presents the results of two 160-190 GHz monolithic low noise amplifiers (LNAs) fabricated with 0.07-microns pseudomorphic (PM) InAlAs/InGaAs/InP HEMT technology using a reactive ion etch (RIE) via hole process. A peak small signal gain of 9 dB was measured at 188 GHz for the first LNA with a 3-dB bandwidth from 164 to 192 GHz while the second LNA has achieved over 6-dB gain from 142 to 180 GHz. The same design (second LNA) was also fabricated with 0.08-micron gate and a wet etch process, showing a small signal gain of 6 dB with noise figure 6 dB. All the measurement results were obtained via on-wafer probing. The LNA noise measurement at 170 GHz is also the first attempt at this frequency.

Kok, Y. L.↗