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39 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Planarization of p -GaN surfaces on MOCVD grown V-defect engineered GaN-based LEDs

The large polarization barriers between the quantum wells and quantum barriers in long-wavelength GaN-based light-emitting diodes (LEDs) inhibit their performance by requiring excess driving voltages to reach standard operating current densities. Lateral injection of carriers directly into quantum wells is required to circumvent this issue. V-defects are naturally occurring inverted hexagonal defects with semipolar {$10\bar{1}1$}-plane sidewalls generated on surface depressions from threading dislocations. LEDs engineered to intentionally generate V-defects below the active region of the LED can achieve lateral carrier injection through the V-defect sidewalls and have already been able to demonstrate world record wall-plug efficiencies for LEDs in the green-red wavelengths. V-defects can be enlarged during kinetically limited growth where the growth rate of the c-plane GaN is faster than that of their sidewalls, leaving them unfilled. We report on the metal organic chemical vapor deposition growth conditions required to fill in V-defects with p-GaN during epitaxial growth of the LED post the active region. Circular transmission length measurements of Pd/Au contacts processed on p-GaN surfaces with various amounts of unfilled V-defects showed no significant difference in their sheet resistance and specific contact resistance. J–V measurements of LEDs grown with varying unfilled V-defect densities showed no significant difference in the forward bias regime. However, in the reverse bias regime, catastrophic breakdown occurred at markedly lower voltages for samples with larger unfilled V-defect densities. This suggests that unfilled V-defects may act as hotspots for device failure, and planarizing LED surfaces may help prevent early degradation of LED devices.

Chemical vapor deposition↗
NASA NTRS2006

Four-Quadrant Analog Multipliers Using G4-FETs

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Mojarradi, Mohammad↗
NASA NTRS2012

Evaluating Nighttime CALIOP 0.532 micron Aerosol Optical Depth and Extinction Coefficient Retrievals

NASA Cloud Aerosol Lidar with Orthogonal Polarization (CALIOP) Version 3.01 5-km nighttime 0.532 micron aerosol optical depth (AOD) datasets from 2007 are screened, averaged and evaluated at 1 deg X 1 deg resolution versus corresponding/co-incident 0.550 micron AOD derived using the US Navy Aerosol Analysis and Prediction System (NAAPS), featuring two-dimensional variational assimilation of quality-assured NASA Moderate Resolution Imaging Spectroradiometer (MODIS) and Multi-angle Imaging Spectroradiometer (MISR) AOD. In the absence of sunlight, since passive radiometric AOD retrievals rely overwhelmingly on scattered radiances, the model represents one of the few practical global estimates available from which to attempt such a validation. Daytime comparisons, though, provide useful context. Regional-mean CALIOP vertical profiles of night/day 0.532 micron extinction coefficient are compared with 0.523/0.532 micron ground-based lidar measurements to investigate representativeness and diurnal variability. In this analysis, mean nighttime CALIOP AOD are mostly lower than daytime (0.121 vs. 0.126 for all aggregated data points, and 0.099 vs. 0.102 when averaged globally per normalised 1 deg. X 1 deg. bin), though the relationship is reversed over land and coastal regions when the data are averaged per normalised bin (0.134/0.108 vs. 0140/0.112, respectively). Offsets assessed within single bins alone approach +/- 20 %. CALIOP AOD, both day and night, are higher than NAAPS over land (0.137 vs. 0.124) and equal over water (0.082 vs. 0.083) when averaged globally per normalised bin. However, for all data points inclusive, NAAPS exceeds CALIOP over land, coast and ocean, both day and night. Again, differences assessed within single bins approach 50% in extreme cases. Correlation between CALIOP and NAAPS AOD is comparable during both day and night. Higher correlation is found nearest the equator, both as a function of sample size and relative signal magnitudes inherent at these latitudes. Root mean square deviation between CALIOP and NAAPS varies between 0.1 and 0.3 globally during both day/night. Averaging of CALIOP along-track AOD data points within a single NAAPS grid bin improves correlation and RMSD, though day/night and land/ocean biases persist and are believed systematic. Vertical profiles of extinction coefficient derived in the Caribbean compare well with ground-based lidar observations, though potentially anomalous selection of a priori lidar ratios for CALIOP retrievals is likely inducing some discrepancies. Mean effective aerosol layer top heights are stable between day and night, indicating consistent layer-identification diurnally, which is noteworthy considering the potential limiting effects of ambient solar noise during day.

aerosol optical depth↗