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At least 55 records · Page 3

Standard Transistor Array (STAR). Volume 2: Test pattern generation

Testing of large scale integrated logic circuits is considered from the point-of-view of automatic test pattern generation. A logic simulator based approach for automatic test pattern generation is taken and is described. The logic model and the timing model used in the simulator are also described. Two methods are presented for generating test patterns from the output of the simulator. Recommendations for future study are also presented.

Carroll, B. D.↗

Enhanced Switching Reliability of Hf 0.5 Zr 0.5 O 2 Ferroelectric Films Induced by Interface Engineering

Ferroelectric materials have been widely researched for applications in memory and energy storage. Among these materials and benefiting from their excellent chemical compatibility with complementary metal–oxide–semiconductor (CMOS) devices, hafnia-based ferroelectric thin films hold great promise for highly scaled semiconductor memories, including nonvolatile ferroelectric capacitors and transistors. However, variation in the switched polarization of this material during field cycling and a limited understanding of the responsible mechanisms have impeded their implementation in technology. Here, we show that ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) capacitors that are nearly free of polarization “wake-up”─a gradual increase in switched polarization as a function of the number of switching cycles─can be achieved by introducing ultrathin HfO 2 buffer layers at the HZO/electrodes interface. High-resolution transmission electron microscopy (HRTEM) reveals crystallite sizes substantially greater than the film thickness for the buffer layer capacitors, indicating that the presence of the buffer layers influences the crystallization of the film (e.g., a lower ratio of nucleation rate to growth rate) during postdeposition annealing. This evidently promotes the formation of a polar orthorhombic (O) phase in the as-fabricated buffer layer samples. Synchrotron X-ray diffraction (XRD) reveals the conversion of the nonpolar tetragonal (T) phase to the polar orthorhombic (O) phase during electric field cycling in the control (no buffer) devices, consistent with the polarization wake-up observed for these capacitors. The extent of T–O transformation in the nonbuffer samples is directly dependent on the duration over which the field is applied. Here these results provide insight into the role of the HZO/electrodes interface in the performance of hafnia-based ferroelectrics and the mechanisms driving the polarization wake-up effect.

36 MATERIALS SCIENCE↗

Automatic hardware synthesis

The complexity of the circuit that can fit on an integrated circuit (IC) chip has reached the level of a million transistors with the advent of Very-Large-Scale Integration (VLSI). Several automatic synthesis systems have evolved that 'aid' the human designer in managing this complexity. This paper surveys such efforts. The synthesis is viewed as the process of transforming a high-level design specification into a lower level design specification that includes more structural details, leading to the physical design of the IC. The characteristics of ten automatic synthesis systems are summarized.

Shiva, S. G.↗

Design and Modeling of the Charge Readout of a SiMOS Quantum Dot with a Single Electron Transistor and CryoCMOS

Single electron spin qubits trapped in SiMOS quantum dots are a promising technology for scaling to thousand- or million-qubit systems due to their compatibility with mature CMOS manufacturing processes. A readout system that combines a single electron transistor with a custom cryogenic CMOS amplification and digitization chain offers key advantages by avoiding the use of bulky RF components or room-temperature interconnects. We present design techniques and simulation results for an optimized qubit-SET cryoCMOS interface, culminating in the design of the QNDR1 ASIC, the first cryogenic readout ASIC designed under the Quandarum project, which targets the development of a many-channel spin qubit based detector for use in high energy physics.

Quinn, Adam [Fermilab] (ORCID:0009000605056371)↗

One-Step Transfer of Symmetric and Asymmetric Contacts for Large-Scale 2D Electronics and Optoelectronics

Two-dimensional (2D) semiconductors are highly promising candidates for thin-film transistor applications due to their scalability, transferability, atomic thickness, and relatively high carrier mobility. However, a substantial performance gap remains between individual devices based on single-crystalline 2D films and wafer-scale integrated circuits, primarily due to defects introduced during conventional fabrication processes. Here, we report a diamond-assisted electrode transfer technique for the van der Waals integration of wafer-scale prefabricated electrode arrays onto 2D materials, enabling scalable electronics and optoelectronics. Implemented on metal–organic chemical vapor deposition-grown monolayer molybdenum disulfide, this method forms ultraclean metal–semiconductor interfaces, yielding field-effect transistors with excellent ohmic contacts, a low contact resistance of 400 Ω·μm, and a Schottky barrier height of only 9 meV. Furthermore, we demonstrate a scalable transistor array on monolayer molybdenum disulfide with excellent device performance uniformity, achieving an average field-effect mobility of 30 cm 2 V –1 s –1 and an on/off current ratio exceeding 105. Additionally, high photocurrent and responsivity were demonstrated in the array devices, showing their potential for excellent image detection. We further demonstrate the versatility of this technique by fabricating a Schottky diode array through a single-step transfer of asymmetric electrodes─low work function aluminum and high work function gold─onto monolayer tungsten diselenide. This approach provides a clean, effective solution for contact engineering in 2D materials, offering a viable pathway toward wafer-scale, high-performance 2D electronics, optoelectronics, and integrated circuits.

2D electronics↗

Transistor h parameter conversion slide rule

Slide rule enables the ready conversion of transistor h parameters from one form to another and reduces calculation time by a factor of 5 to 10. The scales are selected to cover all ranges of each parameter that will normally exist for any transistor, and answers are given in the correct order of magnitude, making powers-of-ten calculations unnecessary.

Brantner, R. E.↗

Quantum octets in high mobility pentagonal two-dimensional PdSe 2

Two-dimensional (2D) materials have drawn immense interests in scientific and technological communities, owing to their extraordinary properties and their tunability by gating, proximity, strain and external fields. For electronic applications, an ideal 2D material would have high mobility, air stability, sizable band gap, and be compatible with large scale synthesis. Here we demonstrate air stable field effect transistors using atomically thin few-layer PdSe 2 sheets that are sandwiched between hexagonal BN (hBN), with large saturation current > 350 μA/μm, and high field effect mobilities of ~ 700 and 10,000 cm 2 /Vs at 300 K and 2 K, respectively. At low temperatures, magnetotransport studies reveal unique octets in quantum oscillations that persist at all densities, arising from 2-fold spin and 4-fold valley degeneracies, which can be broken by in-plane and out-of-plane magnetic fields toward quantum Hall spin and orbital ferromagnetism.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Dimension scaling effects on the yield sensitivity of HEMT digital circuits

In our previous works, using a graphical tool, yield factor histograms, we studied the yield sensitivity of High Electron Mobility Transistors (HEMT) and HEMT circuit performance with the variation of process parameters. This work studies the scaling effects of process parameters on yield sensitivity of HEMT digital circuits. The results from two HEMT circuits are presented.

Sarker, Jogendra C.↗

Forward-bias tunneling - A limitation to bipolar device scaling

Forward-bias tunneling is observed in heavily doped p-n junctions of bipolar transistors. A simple phenomenological model suitable to incorporation in device codes is developed. The model identifies as key parameters the space-charge-region (SCR) thickness at zero bias and the reduced doping level at its edges which can both be obtained from CV characteristics. This tunneling mechanism may limit the maximum gain achievable from scaled bipolar devices.

Del Alamo, Jesus A.↗

Visualization of Mesoscopic Conductivity Fluctuations in Amorphous Semiconductor Thin-Film Transistors

Charge transport in amorphous semiconductors is considerably more complicated than the process in crystalline materials due to abundant localized states. In addition to device-scale characterization, spatially resolved measurements are important to unveiling electronic properties. Here, we report gigahertz conductivity mapping in amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors by microwave impedance microscopy (MIM), which probes conductivity without Schottky barrier’s influence. The difference between the dc and microwave conductivities reflects the efficacy of the injection barrier in an accumulation-mode transistor. The conductivity exhibits significant nanoscale inhomogeneity in the subthreshold regime, presumably due to trapping and release from localized states. The characteristic length scale of local fluctuations, as determined by the autocorrelation analysis, is about 200 nm. Using a random-barrier model, we can simulate the spatial variation of the potential landscape, which underlies the mesoscopic conductivity distribution. Furthermore, our work provides an intuitive way to understand the charge transport mechanism in amorphous semiconductors at the microscopic level.

36 MATERIALS SCIENCE↗

Development of a wideband wattmeter as a laboratory instrument

A portable, solid state, wideband wattmeter has been developed as a general purpose type of laboratory instrument. Its circuit and component investigations and evaluation data are presented. A prototype unit was used extensively, and served as the basis for a second instrument incorporating refined circuitry and improved packaging. The wattmeter provides true four quadrant operation which permits instantaneous indication of real power as an oscilloscope display. Major performance factors are: frequency bandwidth DC to 1 MHz plus or minus 1 db; current range 10 mA to 100 amperes peak; voltage range 1 volt to 1000 volts peak; accuracy plus or minus 2% of full scale reading. Oscilloscope data for typical switching transients in a transistor inverter circuit are included.

Landes, L. G.↗

"Genetically Engineered" Nanoelectronics

The quantum mechanical functionality of nanoelectronic devices such as resonant tunneling diodes (RTDs), quantum well infrared-photodetectors (QWIPs), quantum well lasers, and heterostructure field effect transistors (HFETs) is enabled by material variations on an atomic scale. The design and optimization of such devices requires a fundamental understanding of electron transport in such dimensions. The Nanoelectronic Modeling Tool (NEMO) is a general-purpose quantum device design and analysis tool based on a fundamental non-equilibrium electron transport theory. NEW was combined with a parallelized genetic algorithm package (PGAPACK) to evolve structural and material parameters to match a desired set of experimental data. A numerical experiment that evolves structural variations such as layer widths and doping concentrations is performed to analyze an experimental current voltage characteristic. The genetic algorithm is found to drive the NEMO simulation parameters close to the experimentally prescribed layer thicknesses and doping profiles. With such a quantitative agreement between theory and experiment design synthesis can be performed.

Klimeck, Gerhard↗

Yearlong 500 C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Silicon carbides↗

Cosmic background radiation anisotropy at degree angular scales - Further results from the South Pole

We report further results from the University of California at Santa Barbara program to measure anisotropy in the cosmic background radiation at angular scales near 1 deg, an angular range corresponding to the largest scales where structure is observed. A 30 GHz high electron mobility transistor amplifier-based detector was coupled to the Advanced Cosmic Microwave Explorer, a 1 m off-axis Gregorian telescope. We present data that represent 64 of the total of 500 hr acquired with this system during the 1990-1991 season. The data have a statistical error of 13.5/micro-K/pixel. These are the smallest error bars of any data set of this type published to date. The data contain a significant signal with a maximum likelihood Delta T/T roughly 1 x 10 exp -5. The spectrum of the signal seen in slightly less than 2 sigma away from the thermal spectrum expected of primordial fluctuations in the cosmic background radiation. If the source of the fluctuations is primordial, then the data are consistent with cold dark matter scenarios when normalized to the large-scale anisotropy observed by COBE, while if the origin of the signal is foreground emission or another form of contaminant then the data are marginally inconsistent with standard cold dark matter models. In either case, the data are sufficiently sensitive to provide a crucial test of many models.

Schuster, Jeffrey↗

Pushing the limits of NAND technology scaling with ferroelectrics

Artificial intelligence (AI) continues to drive transformative advancements across various industries. The data-intensive nature of AI training (and inferencing) has resulted in the generation of unprecedented volumes of data with machine-generated content surpassing human-generated data by more than 100-fold in 2025. Efficiently managing this data influx necessitates advanced digital storage technologies. However, traditional NAND flash memory, which is critical for supporting data flows in AI systems—alongside high-bandwidth memory, for AI training—faces fundamental scaling limitations as it approaches the 1000-layer milestone, encompassing more than 40 trillion transistors. This article delves into the potential of hafnia-based ferroelectric materials as a breakthrough solution to these challenges. Recent advancements indicate that the intrinsic limitations of ferroelectric field-effect transistors (FEFETs) can be mitigated through material and device-level engineering. These advancements enable FEFETs to meet the stringent density, reliability, and scalability requirements of future three-dimensional NAND technology. The role of ferroelectrics in addressing NAND scaling challenges and expanding storage capabilities presents a promising avenue for meeting the storage demands of the AI-driven era.

3D NAND↗

Fabrication of field-effect transistors with transfer-free nanostructured carbon as semiconducting channel material

Carbon nanostructures as active channel material in field effect transistors (FETs) are appealing in microelectronics for their improved performance such as high speed and low energy dissipation. However, these devices require the incorporation of nanostructure transfer steps in the fabrication process flow, which makes difficult its application in large scale integration circuits. Here we present a novel method for the fabrication of FETs with nanostructured carbon in the channel with p-type semiconducting properties and intermediate drain-source current (IDS) on/off ratio. The method is based on the use of Ni nanoparticles in the source-drain gap region as seed material for the formation of carbon nanostructures in the FET channel. FETs without Ni nanoparticles in the channel showed no modulation of IDS as a function of gate voltage. The device fabrication process does not require any carbon nanostructure transfer steps since it directly forms carbon nanostructures electrically connected to the device's source and drain electrodes via electron-beam evaporation of carbon and conventional lithographic processes. Since all device fabrication steps are compatible with Si technology processes, they are capable of being further optimized following process development protocols practiced by the semiconductor industry.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Voltage regulator for solar panels

Shunt voltage regulators for solar panels uses internal resistance of panel to control its output voltage. Regulator can be scaled up for high-current solar panels by adding more transistors.

Casad, T. A.↗

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗