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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 577 records · Page 32
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Spur-Reduced Digital Sinusoid Generation Using Higher-Order Phase Dithering

A higher-order phase dithering technique that reduces the complexity of digital sinusoid generation is presented and analyzed. M(sup th) order phase dithering denotes the addition of M independent, uniform variates to the sinusoid phase prior to word-length reduction. Spurious magnitudes due to quantization effects are accelerated from the usual -6 dBc per phase bit to -6(M + 1) dBc per phase bit, while the noise power increases linearly in M. For a given spurious specification, higher-order phase dithering permits the use of fewer phase bits than the non-dithered system, resulting in an exponential reduction in look-up table size, dramatically decreasing system complexity.

digital sinusoid generation higher-order phase dit↗
NASA NTRS2006

Ultrasonic/Sonic Driller/Corer (USDC) as a Subsurface Sampler and Sensors Platform for Planetary Exploration Applications

The search for existing or past life in the Universe is one of the most important objectives of NASA's mission. For this purpose, effective instruments that can sample and conduct in-situ astrobiology analysis are being developed. In support of this objective, a series of novel mechanisms that are driven by an Ultrasonic/Sonic actuator have been developed to probe and sample rocks, ice and soil. This mechanism is driven by an ultrasonic piezoelectric actuator that impacts a bit at sonic frequencies through the use of an intermediate free-mass. Ultrasonic/Sonic Driller/Corer (USDC) devices were made that can produce both core and powdered cuttings, operate as a sounder to emit elastic waves and serve as a platform for sensors. For planetary exploration, this mechanism has the important advantage of requiring low axial force, virtually no torque, and can be duty cycled for operation at low average power. The advantage of requiring low axial load allows overcoming a major limitation of planetary sampling in low gravity environments or when operating from lightweight robots and rovers. The ability to operate at duty cycling with low average power produces a minimum temperature rise allowing for control of the sample integrity and preventing damage to potential biological markers in the acquired sample. The development of the USDC is being pursued on various fronts ranging from analytical modeling to mechanisms improvements while considering a wide range of potential applications. While developing the analytical capability to predict and optimize its performance, efforts are made to enhance its capability to drill at higher power and high speed. Taking advantage of the fact that the bit does not require rotation, sensors (e.g., thermocouple and fiberoptics) were integrated into the bit to examine the borehole during drilling. The sounding effect of the drill was used to emit elastic waves in order to evaluate the surface characteristics of rocks. Since the USDC is driven by piezoelectric actuation mechanism it can designed to operate at extreme temperature environments from very cold as on Titan and Europa to very hot as on Venus. In this paper, a review of the latest development and applications of the USDC will be given.

sampling↗
NASA NTRS2007

Self Mountable and Extractable Ultrasonic/Sonic Anchor

Self drilling anchors and related methods and apparatus. In one embodiment an apparatus comprises a drill bit, a hammer mechanism for hammering the drill bit in a first direction and in a second direction, and a selection mechanism for controlling whether, at a given point in time, the drill bit is hammered in the first or second direction.

Bar-Cohen, Yoseph↗
NASA NTRS2007

Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

MacLeod, Todd C.↗
NASA NTRS2006

Coherent Optical Focal Plane Array Receiver for PPM Signals: Investigation and Applications

The performance of a coherent optical focal plane array receiver for PPM signals under atmospheric turbulence is investigated and applications of this system are addressed. The experimental demonstration of this project has already been explained in previous publications [1]. This article shows a more exhaustive analysis of the expressions needed to obtain the Bit Error Rate (BER) for the real system under study in the laboratory. Selected experimental results of this system are described and compared with theoretical BER expressions, and array combining gains are presented. Receiver sensitivity in terms of photons per bit (PPB) is examined; BER results are shown as a function of signal to noise ratios, (SNR), as well as a function of photons per symbol, and photons per bit.

shot noise limited↗
NASA NTRS1996

Video event trigger and tracking system using fuzzy comparators

A video observation method and apparatus, the apparatus having a frame storage mechanism, a dividing mechanism, a plurality of fuzzy comparators and a trigger signal mechanism. The frame storage mechanism stores at least one non-current video frame of a viewing field. The dividing mechanism divides a current video frame of the viewing field and the at least one non-current video frame into a plurality of corresponding trigger sections. The plurality of fuzzy comparators each compare and detect a fuzzy logic difference between one trigger section of the current video frame and the corresponding trigger sections of the at least one non-current video frame, the number of fuzzy comparators being selected so that every trigger section of the current video frame is compared. The trigger signal mechanism provides a trigger signal when a fuzzy logic difference is detected between any of the corresponding current and non-current trigger sections. A video observation mechanism and data reducing mechanism may be included with the above apparatus or alone with only a frame storage mechanism, a single generic comparator and a trigger signal mechanism. The video observation mechanism provides a video data stream, wherein each pixel of each frame of a viewing field is provided as multiple bits of data. The data reducing mechanism reduces each set of multiple bits of data which correspond to each pixel to one bit of binary data based on whether the pixel has a level of grey which is above or below a threshold level of grey.

Williams, Glenn L.↗
NASA NTRS2006

Network device interface for digitally interfacing data channels to a controller via a network

The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is then converted into digital signals and transmitted back to the controller. In one embodiment, the bus controller sends commands and data a defined bit rate, and the network device interface senses this bit rate and sends data back to the bus controller using the defined bit rate.

Ellerbrock, Philip J.↗
NASA NTRS1990

Multiple trellis coded modulation

A technique for designing trellis codes to minimize bit error performance for a fading channel. The invention provides a criteria which may be used in the design of such codes which is significantly different from that used for average white Gaussian noise channels. The method of multiple trellis coded modulation of the present invention comprises the steps of: (a) coding b bits of input data into s intermediate outputs; (b) grouping said s intermediate outputs into k groups of s.sub.i intermediate outputs each where the summation of all s.sub.i,s is equal to s and k is equal to at least 2; (c) mapping each of said k groups of intermediate outputs into one of a plurality of symbols in accordance with a plurality of modulation schemes, one for each group such that the first group is mapped in accordance with a first modulation scheme and the second group is mapped in accordance with a second modulation scheme; and (d) outputting each of said symbols to provide k output symbols for each b bits of input data.

Simon, Marvin K.↗
NASA NTRS1989

Unsymmetrical QPSK demodulator

The present invention is a demodulator for demodulating an unsymmetrical QPSK signal (1), i.e., one in which the amplitudes of the I and Q channels are different, and the I and Q channels have been modulated by signals having differnt bit rates. Analog versions of the I and Q modulating baseband signals are first extracted from the carrier. Each baseband signal is then subjected to a bit-rate-matched low pass filter (23, 13). The channel having the higher bit rate is subjected to a delay (32) to time-align the two baseband signals. The time-aligned filtered signals are then amplified by amplifiers (22, 12) having unequal gains that are preselected to substantially equalize the amplifier (22, 12) outputs. The amplified time-aligned filtered signals are then subjected to a phase error (E) generating means (15, 25, 16, 26, 34). The phase error (E) is passed through a loop integrator (38) and a VCO (30) and back to the baseband signal extracting means to complete a phase lock loop. Frequency searching means (40), frequency lock detect means (42, 44), and AGC control ( 46, 8) are optionally present.

Guyer, Edward↗
NASA NTRS2008

High-Density, High-Bandwidth, Multilevel Holographic Memory

A proposed holographic memory system would be capable of storing data at unprecedentedly high density, and its data transfer performance in both reading and writing would be characterized by exceptionally high bandwidth. The capabilities of the proposed system would greatly exceed even those of a state-of-the art memory system, based on binary holograms (in which each pixel value represents 0 or 1), that can hold .1 terabyte of data and can support a reading or writing rate as high as 1 Gb/s. The storage capacity of the state-of-theart system cannot be increased without also increasing the volume and mass of the system. However, in principle, the storage capacity could be increased greatly, without significantly increasing the volume and mass, if multilevel holograms were used instead of binary holograms. For example, a 3-bit (8-level) hologram could store 8 terabytes, or an 8-bit (256-level) hologram could store 256 terabytes, in a system having little or no more size and mass than does the state-of-the-art 1-terabyte binary holographic memory. The proposed system would utilize multilevel holograms. The system would include lasers, imaging lenses and other beam-forming optics, a block photorefractive crystal wherein the holograms would be formed, and two multilevel spatial light modulators in the form of commercially available deformable-mirror-device spatial light modulators (DMDSLMs) made for use in high speed input conversion of data up to 12 bits. For readout, the system would also include two arrays of complementary metal oxide/semiconductor (CMOS) photodetectors matching the spatial light modulators. The system would further include a reference-beam sterring device (equivalent of a scanning mirror), containing no sliding parts, that could be either a liquid-crystal phased-array device or a microscopic mirror actuated by a high-speed microelectromechanical system. Time-multiplexing and the multilevel nature of the DMDSLM would be exploited to enable writing and reading of multilevel holograms. The DMDSLM would also enable transfer of data at a rate of 7.6 Gb/s or perhaps somewhat higher.

Chao, Tien-Hsin↗
NASA NTRS2009

LDPC-PPM Coding Scheme for Optical Communication

In a proposed coding-and-modulation/demodulation-and-decoding scheme for a free-space optical communication system, an error-correcting code of the low-density parity-check (LDPC) type would be concatenated with a modulation code that consists of a mapping of bits to pulse-position-modulation (PPM) symbols. Hence, the scheme is denoted LDPC-PPM. This scheme could be considered a competitor of a related prior scheme in which an outer convolutional error-correcting code is concatenated with an interleaving operation, a bit-accumulation operation, and a PPM inner code. Both the prior and present schemes can be characterized as serially concatenated pulse-position modulation (SCPPM) coding schemes. Figure 1 represents a free-space optical communication system based on either the present LDPC-PPM scheme or the prior SCPPM scheme. At the transmitting terminal, the original data (u) are processed by an encoder into blocks of bits (a), and the encoded data are mapped to PPM of an optical signal (c). For the purpose of design and analysis, the optical channel in which the PPM signal propagates is modeled as a Poisson point process. At the receiving terminal, the arriving optical signal (y) is demodulated to obtain an estimate (a^) of the coded data, which is then processed by a decoder to obtain an estimate (u^) of the original data.

Barsoum, Maged↗
NASA NTRS2010

Fully Printed High-Frequency Phased-Array Antenna on Flexible Substrate

To address the issues of flexible electronics needed for surface-to-surface, surface-to-orbit, and back-to-Earth communications necessary for manned exploration of the Moon, Mars, and beyond, a room-temperature printing process has been developed to create active, phased-array antennas (PAAs) on a flexible Kapton substrate. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proven feasible for phased-array antenna systems. The carrier mobility of an individual CNT is estimated to be at least 100,000 sq cm/V(dot)s. The CNT network in solution has carrier mobility as high as 46,770 sq cm/V(dot)s, and has a large current-density carrying capacity of approx. 1,000 mA/sq cm , which corresponds to a high carrying power of over 2,000 mW/ sq cm. Such high carrier mobility, and large current carrying capacity, allows the achievement of high-speed (>100 GHz), high-power, flexible electronic circuits that can be monolithically integrated on NASA s active phasedarray antennas for various applications, such as pressurized rovers, pressurized habitats, and spacesuits, as well as for locating beacon towers for lunar surface navigation, which will likely be performed at S-band and attached to a mobile astronaut. A fully printed 2-bit 2-element phasedarray antenna (PAA) working at 5.6 GHz, incorporating the CNT FETs as phase shifters, is demonstrated. The PAA is printed out at room temperature on 100-mm thick Kapton substrate. Four CNT FETs are printed together with microstrip time delay lines to function as a 2-bit phase shifter. The FET switch exhibits a switching speed of 0.2 ns, and works well for a 5.6-GHz RF signal. The operating frequency is measured to be 5.6 GHz, versus the state-of-the-art flexible FET operating frequency of 52 MHz. The source-drain current density is measured to be over 1,000 mA/sq cm, while the conventional organic FETs, and single carbon nanotube-based FETs, are typically in the mA to mA/sq cm range. The switching voltage used is 1.8 V, while the state-of-the-art flexible FET has a gate voltage around 50 V. The gate voltage can effectively control the source-drain current with an ON-OFF ratio of over 1,000 obtained at a low Vds bias of 1.8 V. The azimuth steering angles of PAA are measured at 0deg, -14.5deg, -30deg, and 48.6deg. The measured far-field patterns agree well with simulation results. The efficiency of the 2-bit 2-element PAA is measured to be 39 percent, including the loss of transmission line, FET switch, and coupling loss of RF probes. With further optimization, the efficiency is expected to be around 50-60 percent.

Chen, Yihong↗
NASA NTRS2011

Single-Frame Terrain Mapping Software for Robotic Vehicles

This software is a component in an unmanned ground vehicle (UGV) perception system that builds compact, single-frame terrain maps for distribution to other systems, such as a world model or an operator control unit, over a local area network (LAN). Each cell in the map encodes an elevation value, terrain classification, object classification, terrain traversability, terrain roughness, and a confidence value into four bytes of memory. The input to this software component is a range image (from a lidar or stereo vision system), and optionally a terrain classification image and an object classification image, both registered to the range image. The single-frame terrain map generates estimates of the support surface elevation, ground cover elevation, and minimum canopy elevation; generates terrain traversability cost; detects low overhangs and high-density obstacles; and can perform geometry-based terrain classification (ground, ground cover, unknown). A new origin is automatically selected for each single-frame terrain map in global coordinates such that it coincides with the corner of a world map cell. That way, single-frame terrain maps correctly line up with the world map, facilitating the merging of map data into the world map. Instead of using 32 bits to store the floating-point elevation for a map cell, the vehicle elevation is assigned to the map origin elevation and reports the change in elevation (from the origin elevation) in terms of the number of discrete steps. The single-frame terrain map elevation resolution is 2 cm. At that resolution, terrain elevation from 20.5 to 20.5 m (with respect to the vehicle's elevation) is encoded into 11 bits. For each four-byte map cell, bits are assigned to encode elevation, terrain roughness, terrain classification, object classification, terrain traversability cost, and a confidence value. The vehicle s current position and orientation, the map origin, and the map cell resolution are all included in a header for each map. The map is compressed into a vector prior to delivery to another system.

Rankin, Arturo L.↗
NASA NTRS2005

Scheme for Entering Binary Data Into a Quantum Computer

A quantum algorithm provides for the encoding of an exponentially large number of classical data bits by use of a smaller (polynomially large) number of quantum bits (qubits). The development of this algorithm was prompted by the need, heretofore not satisfied, for a means of entering real-world binary data into a quantum computer. The data format provided by this algorithm is suitable for subsequent ultrafast quantum processing of the entered data. Potential applications lie in disciplines (e.g., genomics) in which one needs to search for matches between parts of very long sequences of data. For example, the algorithm could be used to encode the N-bit-long human genome in only log2N qubits. The resulting log2N-qubit state could then be used for subsequent quantum data processing - for example, to perform rapid comparisons of sequences.

Williams, Colin↗
NASA NTRS2005

Optimizing Parameters for Deep-Space Optical Communication

A paper discusses the optimization of the parameters of a high-rate, deep-space optical communication link that utilizes pulse-position modulation (PPM) and an error-correcting code (ECC). The parameters in question include the PPM order (number of pulse time slots in one symbol period), the ECC rate, and the uncoded symbol error rate. In simple terms, the optimization problem is to choose the combination of these parameters that maximizes the throughput data rate at a given bit-error-rate (BER), subject to several constraints, including limits on the average and peak power and possibly a limit on the uncoded symbol error rate. This is a complex, multidimensional optimization problem, the solution of which involves computation of channel capacities for various combinations of the parameters. The paper presents extensive theoretical analyses and numerical predictions that elucidate the many facets of the optimization problem. It shows how a nearly optimum solution can be obtained by choosing the optimum PPM order for the desired number of bits per slot and concatenating the PPM mapping with an error-correction code so that the decoded bits satisfy some BER threshold.

Moison, Bruce↗
NASA NTRS2004

Reduction of Phase Ambiguity in an Offset-QPSK Receiver

Proposed modifications of an offset-quadri-phase-shift keying (offset-QPSK) transmitter and receiver would reduce the amount of signal processing that must be done in the receiver to resolve the QPSK fourfold phase ambiguity. Resolution of the phase ambiguity is necessary in order to synchronize, with the received carrier signal, the signal generated by a local oscillator in a carrier-tracking loop in the receiver. Without resolution of the fourfold phase ambiguity, the loop could lock to any of four possible phase points, only one of which has the proper phase relationship with the carrier. The proposal applies, more specifically, to an offset-QPSK receiver that contains a carrier-tracking loop like that shown in Figure 1. This carrier-tracking loop does not resolve or reduce the phase ambiguity. A carrier-tracking loop of a different design optimized for the reception of offset QPSK could reduce the phase ambiguity from fourfold to twofold, but would be more complex. Alternatively, one could resolve the fourfold phase ambiguity by use of differential coding in the transmitter, at a cost of reduced power efficiency. The proposed modifications would make it possible to reduce the fourfold phase ambiguity to twofold, with no loss in power efficiency and only relatively simple additional signal-processing steps in the transmitter and receiver. The twofold phase ambiguity would then be resolved by use of a unique synchronization word, as is commonly done in binary phase-shift keying (BPSK). Although the mathematical and signal-processing principles underlying the modifications are too complex to explain in detail here, the modifications themselves would be relatively simple and are best described with the help of simple block diagrams (see Figure 2). In the transmitter, one would add a unit that would periodically invert bits going into the QPSK modulator; in the receiver, one would add a unit that would effect different but corresponding inversions of bits coming out of the QPSK demodulator. The net effect of all the inversions would be that depending on which lock point the carrier-tracking loop had selected, all the output bits would be either inverted or non-inverted together; hence, the ambiguity would be reduced from fourfold to twofold, as desired.

Berner, Jeff↗
NASA NTRS2004

Coding for Communication Channels with Dead-Time Constraints

Coding schemes have been designed and investigated specifically for optical and electronic data-communication channels in which information is conveyed via pulse-position modulation (PPM) subject to dead-time constraints. These schemes involve the use of error-correcting codes concatenated with codes denoted constrained codes. These codes are decoded using an interactive method. In pulse-position modulation, time is partitioned into frames of Mslots of equal duration. Each frame contains one pulsed slot (all others are non-pulsed). For a given channel, the dead-time constraints are defined as a maximum and a minimum on the allowable time between pulses. For example, if a Q-switched laser is used to transmit the pulses, then the minimum allowable dead time is the time needed to recharge the laser for the next pulse. In the case of bits recorded on a magnetic medium, the minimum allowable time between pulses depends on the recording/playback speed and the minimum distance between pulses needed to prevent interference between adjacent bits during readout. The maximum allowable dead time for a given channel is the maximum time for which it is possible to satisfy the requirement to synchronize slots. In mathematical shorthand, the dead-time constraints for a given channel are represented by the pair of integers (d,k), where d is the minimum allowable number of zeroes between ones and k is the maximum allowable number of zeroes between ones. A system of the type to which the present schemes apply is represented by a binary- input, real-valued-output channel model illustrated in the figure. At the transmitting end, information bits are first encoded by use of an error-correcting code, then further encoded by use of a constrained code. Several constrained codes for channels subject to constraints of (d,infinity) have been investigated theoretically and computationally. The baseline codes chosen for purposes of comparison were simple PPM codes characterized by M-slot PPM frames separated by d-slot dead times.

Moision, Bruce↗
NASA NTRS2004

FPGA-Based, Self-Checking, Fault-Tolerant Computers

A proposed computer architecture would exploit the capabilities of commercially available field-programmable gate arrays (FPGAs) to enable computers to detect and recover from bit errors. The main purpose of the proposed architecture is to enable fault-tolerant computing in the presence of single-event upsets (SEUs). [An SEU is a spurious bit flip (also called a soft error) caused by a single impact of ionizing radiation.] The architecture would also enable recovery from some soft errors caused by electrical transients and, to some extent, from intermittent and permanent (hard) errors caused by aging of electronic components. A typical FPGA of the current generation contains one or more complete processor cores, memories, and highspeed serial input/output (I/O) channels, making it possible to shrink a board-level processor node to a single integrated-circuit chip. Custom, highly efficient microcontrollers, general-purpose computers, custom I/O processors, and signal processors can be rapidly and efficiently implemented by use of FPGAs. Unfortunately, FPGAs are susceptible to SEUs. Prior efforts to mitigate the effects of SEUs have yielded solutions that degrade performance of the system and require support from external hardware and software. In comparison with other fault-tolerant- computing architectures (e.g., triple modular redundancy), the proposed architecture could be implemented with less circuitry and lower power demand. Moreover, the fault-tolerant computing functions would require only minimal support from circuitry outside the central processing units (CPUs) of computers, would not require any software support, and would be largely transparent to software and to other computer hardware. There would be two types of modules: a self-checking processor module and a memory system (see figure). The self-checking processor module would be implemented on a single FPGA and would be capable of detecting its own internal errors. It would contain two CPUs executing identical programs in lock step, with comparison of their outputs to detect errors. It would also contain various cache local memory circuits, communication circuits, and configurable special-purpose processors that would use self-checking checkers. (The basic principle of the self-checking checker method is to utilize logic circuitry that generates error signals whenever there is an error in either the checker or the circuit being checked.) The memory system would comprise a main memory and a hardware-controlled check-pointing system (CPS) based on a buffer memory denoted the recovery cache. The main memory would contain random-access memory (RAM) chips and FPGAs that would, in addition to everything else, implement double-error-detecting and single-error-correcting memory functions to enable recovery from single-bit errors.

Some, Raphael↗