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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 577 records · Page 32
All sourcesNASA NTRSDOE OSTI
NASA NTRS1989

Image-Enhancement Aid For The Partially Sighted

Digital filtering enhances ability to read and to recognize objects. Possible to construct portable vision aid by combining miniature video equipment to observe scene and display images with very-large-scale integrated circuits to implement real-time digital image-data processing. Afflicted observer views scene through magnifier to shift spatial frequencies downward and thereby improves perceived image. However, less magnification needed, larger the scene observed. Thus, one measure of effectiveness of new system is amount of magnification required with and without it. In series of tests, found 27 to 70 percent more magnification needed for afflicted observers to recognize unfiltered words than to recognize filtered words.

Lawton, T. A.↗
NASA NTRS2014

High Current ESD Test of Advanced Triple Junction Solar Array Coupon

A test was conducted on an Advanced Triple Junction (ATJ) coupon that was part of a risk reduction effort in the development of a high-powered solar array design by SSL. The ATJ coupon was a small, 4-cell, two-string configuration that has served as the basic test coupon design used in previous SSL environmental aging campaigns. The coupon has many attributes of the flight design; e.g., substrate structure with graphite face sheets, integrated by-pass diodes, cell interconnects, RTV grout, wire routing, etc. The objective of the present test was to evaluate the performance of the coupon after being subjected to induced electrostatic discharge testing at two string voltages (100 V, 150 V) and four array current (1.65 A, 2.0 A, 2.475 A, and 3.3 A). An ESD test circuit, unique to SSL solar array design, was built that simulates the effect of missing cells and strings in a full solar panel with special primary arc flashover circuitry. A total of 73 primary arcs were obtained that included 7 temporary sustained arcs (TSA) events. The durations of the TSAs ranged from 50 μs to 2.9 ms. All TSAs occurred at a string voltage of 150 V. Post-test Large Area Pulsed Solar Simulator (LAPSS), Dark I-V, and By-Pass Diode tests showed that no degradation occurred due to the TSA events. In addition, the post-test insulation resistance measured was > 50 G-ohms between cells and substrate. These test results indicate a robust design for application to a high-current, high-power mission application.

Wright, K. H.↗
NASA NTRS2015

High Current ESD Test of Advanced Triple Junction Solar Array Coupon

A test was conducted on an Advanced Triple Junction (ATJ) coupon that was part of a risk reduction effort in the development of a high-powered solar array design by SSL. The ATJ coupon was a small, 4-cell, two-string configuration that has served as the basic test coupon design used in previous SSL environmental aging campaigns. The coupon has many attributes of the flight design; e.g., substrate structure with graphite face sheets, integrated by-pass diodes, cell interconnects, RTV grout, wire routing, etc. The objective of the present test was to evaluate the performance of the coupon after being subjected to induced electrostatic discharge testing at two string voltages (100 V, 150 V) and four array current (1.65 A, 2.0 A, 2.475 A, and 3.3 A). An ESD test circuit, unique to SSL solar array design, was built that simulates the effect of missing cells and strings in a full solar panel with special primary arc flashover circuitry. A total of 73 primary arcs were obtained that included 7 temporary sustained arcs (TSA) events. The durations of the TSAs ranged from 50 micros to 2.9 ms. All TSAs occurred at a string voltage of 150 V. Post-test Large Area Pulsed Solar Simulator (LAPSS), Dark I-V, and By-Pass Diode tests showed that no degradation occurred due to the TSA events. In addition, the post-test insulation resistance measured was > 50 G-ohms between cells and substrate. These test results indicate a robust design for application to a high-current, high-power mission application.

Wright, Kenneth H., Jr.↗
DOE OSTI2022

A Prototype High-Voltage Pulsed Power Supply for Control of the ITER Shattered Pellet Injection System Flyer Plate Valve

A high-voltage pulsed power supply (HVPPS) has been designed, prototyped, and tested for driving an eddy current actuated propellant valve for the International Thermonuclear Experimental Reactor (ITER) disruption mitigation system. The high-voltage (HV) dc supply output voltage is software programmable, and the energy storage capacitor bank can be readily reconfigured as 200, 400, 600, and 800 μ F, enabling testing and optimization of both the valve drive and valve systems. Multiple system parameters are monitored before, during, and after each firing of the valve. The system parameters are both displayed and stored for further analysis. Control of the setup, firing sequence, and data collection is automated using a LabVIEW-based control program. The programmability and reconfigurability of this system collectively provide a flexible and robust platform for system refinement and optimization. In this article, a summary of the system will be provided including operational sequences, HV switching and associated triggering methods and circuits, and results measured while firing a solid frozen pellet. Additionally, planned refinement activities toward meeting all requirements for ITER integration will be discussed.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2025

PSEC5 Physical Verification

Ultra-Fast timing detectors, having a time resolution of 10pSec or less, are becoming increasingly important for many scientific disciplines, including High Energy Physics, Nuclear Physics, Medical Imaging and more. When developing ultra-fast detectors such as MCPs, LAPPDs, LGADs, SNSPDs, it is necessary to have access to a readout system that is low power, can support many channels and is cost effective. The PSEC5 chip was an application specific integrated circuit (ASIC) developed by the pioneering group of Prof. Henry Frisch at University of Chicago and micro electronic engineers at Fermi National Accelerator Laboratory. Three boards were designed, two to implement the readout system for an LAPPD and one to only characterize the PSEC1 chip. The main goal of the project shifted to setting up a testing environment to focus on the characterization of the chip. My student and I tested and characterized this ASIC using the third chip-on-board printed circuit board. Results show the successful fabrication and operation of some of the key building blocks and lead to the suggestions on modification for the second iteration of the chip.

Rico Aniles, H. D. [Unlisted]↗
NASA NTRS1983

IPACS Electronics: Comments on the Original Design and Current Efforts at Langley Research Center

The development of the integrated power altitude control system (IPACS) is described. The power bridge was fabricated, and all major parts are in hand. The bridge was tested with a 1/4 HP motor for another program. The PWM, Control Logic, and upper bridge driver power supply are breadboarded and are debugged prior to starting testing on a passive load. The Hall sensor circuit for detecting rotor position is in design.

Gowdey, J. C.↗
NASA NTRS1987

System architecture of a gallium arsenide one-gigahertz digital IC tester

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

Fouts, Douglas J.↗
NASA NTRS2014

High Current ESD Test of Advanced Triple Junction Solar Array Coupon

Testing was conducted on an Advanced Triple Junction (ATJ) coupon that was part of a risk reduction effort in the development of a high-powered solar array design by Space Systems/Loral, LLC (SSL). The ATJ coupon was a small, 4-cell, two-string configuration that has served as the basic test coupon design used in previous SSL environmental aging campaigns. The coupon has many attributes of the flight design; e.g., substrate structure with graphite face sheets, integrated by-pass diodes, cell interconnects, RTV grout, wire routing, etc. The objective of the present test was to evaluate the performance of the coupon after being subjected to induced electrostatic discharge (ESD) testing at two string voltages (100 V, 150 V) and four array currents (1.65 A, 2.0 A, 2.475 A, and 3.3 A). An ESD test circuit, unique to SSL solar array design, was built that simulates the effect of missing cells and strings in a full solar panel with special primary arc flashover circuitry. A total of 73 primary arcs were obtained that included 7 temporary sustained arcs (TSA) events. The durations of the TSAs ranged from 50 micro-seconds to 2.75 milli-seconds. All TSAs occurred at a string voltage of 150 V. Post-test Large Area Pulsed Solar Simulator (LAPSS), Dark I-V, and By-Pass Diode tests showed that no degradation occurred due to the TSA events. In addition, the post-test insulation resistance measured was > 50 G-ohms between cells and substrate. These test results indicate a robust design for application to a high-current, high-power mission.

Wright, Kenneth H., Jr.↗
NASA NTRS1985

Processing technology for high efficiency silicon solar cells

Recent advances in silicon solar cell processing have led to attainment of conversion efficiency approaching 20%. The basic cell design is investigated and features of greatest importance to achievement of 20% efficiency are indicated. Experiments to separately optimize high efficiency design features in test structures are discussed. The integration of these features in a high efficiency cell is examined. Ion implantation has been used to achieve optimal concentrations of emitter dopant and junction depth. The optimization reflects the trade-off between high sheet conductivity, necessary for high fill factor, and heavy doping effects, which must be minimized for high open circuit voltage. A second important aspect of the design experiments is the development of a passivation process to minimize front surface recombination velocity. The manner in which a thin SiO2 layer may be used for this purpose is indicated without increasing reflection losses, if the antireflection coating is properly designed. Details are presented of processing intended to reduce recombination at the contact/Si interface. Data on cell performance (including CZ and ribbon) and analysis of loss mechanisms are also presented.

Spitzer, M. B.↗
NASA NTRS1989

Asymmetrical SRAM Cells For Radiation Tests

Features of circuits altered to increase or decrease sensitivity to radiation. State-space analysis used to analyze single-event-upset behavior of memory cell. When voltage on node a is set at one of indicated initial values Vao and then released, voltages on nodes a and b then follow indicated trajectory to final logic "one" or logic "zero" state. Ability to do this important for design of radiation-detecting integrated circuits (deliberately made more sensitive to ionizing radiation) and "radiation-hardened" integrated circuits - those intended to be relatively invulnerable to intense radiation.

Buehler, Martin G.↗
NASA NTRS1995

Improved Speed Control System for the 87,000 HP Wind Tunnel Drive

This paper describes the design, installation, and integrated systems tests for a new drive motor speed control system which was part of a recent rehab project for the NASA Lewis 8x6 Supersonic Wind Tunnel. The tunnel drive consists of three mechanically-coupled 29,000 HP wound rotor induction motors driving an axial flow compressor. Liquid rheostats are used to vary the impedance of the rotor circuits, thus varying the speed of the drive system. The new design utilizes a distributed digital control system with a dual touch screen CRT operator console to provide alarm monitoring, logging, and trending. The liquid rheostats are driven by brushtype servomotor systems with magnetostrictive linear displacement transducers used for position feedback. The new system achieved all goals for speed variations with load, motor load balance, and control of total power.

Becks, Edward A.↗
NASA NTRS2007

MMIC Amplifiers for 90 to 130 GHz

This brief describes two monolithic microwave integrated-circuit (MMIC) amplifier chips optimized to function in the frequency range of 90 to 130 GHz, covering nearly all of F-band (90 - 140 GHz). These amplifiers were designed specifically for local-oscillator units in astronomical radio telescopes such as the Atacama Large Millimeter Array (ALMA). They could also be readily adapted for use in electronic test equipment, automotive radar systems, and communications systems that operate between 90 and 130 GHz.

Samoska, Lorene↗
DOE OSTI2020

Comparison of Hafnium Dioxide and Zirconium Dioxide Grown by Plasma-Enhanced Atomic Layer Deposition for the Application of Electronic Materials

We report the growth of nanoscale hafnium dioxide (HfO 2 ) and zirconium dioxide (ZrO 2 ) thin films using remote plasma-enhanced atomic layer deposition (PE-ALD), and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using the HfO 2 and ZrO 2 thin films as the gate oxide. Tetrakis (dimethylamino) hafnium (Hf[N(CH 3 ) 2 ] 4 ) and tetrakis (dimethylamino) zirconium (IV) (Zr[N(CH 3 ) 2 ] 4 ) were used as the precursors, while O 2 gas was used as the reactive gas. The PE-ALD-grown HfO 2 and ZrO 2 thin films were analyzed using X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), and high-resolution transmission electron microscopy (HRTEM). The XPS measurements show that the ZrO 2 film has the atomic concentrations of 34% Zr, 2% C, and 64% O while the HfO 2 film has the atomic concentrations of 29% Hf, 11% C, and 60% O. The HRTEM and XRD measurements show both HfO 2 and ZrO 2 films have polycrystalline structures. n-channel and p-channel metal-oxide semiconductor field-effect transistors (nFETs and pFETs), CMOS inverters, and CMOS ring oscillators were fabricated to test the quality of the HfO 2 and ZrO 2 thin films as the gate oxide. Current-voltage (IV) curves, transfer characteristics, and oscillation waveforms were measured from the fabricated transistors, inverters, and oscillators, respectively. The experimental results measured from the HfO 2 and ZrO 2 thin films were compared.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
NASA NTRS1982

Cost effective development of a Shuttle-based astronomical instrument control system

The high level language FORTH is used for the electronic control of the Space Shuttle-based Ultraviolet Imaging Telescope, in a flight computer system which minimizes costs. The greater part of the breadboard version of the flight computer is assembled from commercially available components, reducing novel circuit design features and permitting simultaneous development of both hardware and software. The commercial boards are then refabricated on aluminum core heat conducting stock, using high reliability parts to produce the flight versions of the system. The system's ground support equipment employs a MINC-25 minicomputer which performs such functions as flight computer software development, PROM programming, test and integration support, and flight operations support. The implementation of these concepts in flight computer telescope controls is described.

Parise, R. A.↗
DOE OSTI2024

Comparative Analysis of Heat Exchangers for High Temperature High Pressure Helium Component Testing

Helium gas loops have been designed and built to gain a better understanding of the gas thermohydraulic phenomena that take place in a helium system. Some of these loops are used for validation and testing of components for high temperature gas-cooled reactors (HTGRs). However, most of them operate at lower pressure and temperature than an HTGR. While these loops can provide valuable information about gas-cooled reactor components, the operating envelope of the experiment is constrained by the maximum operating conditions of the helium loop. In response to the lack of an experimental facility that can provide the infrastructure needed to validate and test components at nominal pressures and temperatures of HTGRS, the HElium Component Testing Out-of-pile Research (HECTOR) facility was designed at Idaho National Laboratory with the assistance of University of Idaho and Walsh Engineering. With the capability to test at temperatures up to 800°C and pressures of 8MPa, HECTOR serves as a critical tool for the advancement of HTGR technology. The facility's primary role is to provide a controlled, high-fidelity environment for the assessment of component resilience and efficiency under nominal HTGR conditions. In the quest to enhance the efficiency and performance of HECTOR, a comparative analysis of three distinct types of heat exchangers—shell and tube, offset strip fin, and printed-circuit—was conducted, focusing primarily on two critical metrics: the required surface area and pressure drop characteristics. The shell and tube heat exchanger, renowned for its robust design and widespread industrial application, was evaluated against the offset strip fin and the cuttingedge printed-circuit heat exchangers, both of which are lauded for their compactness and thermal effectiveness. This comparative study aims to provide detailed insights into the thermal management capabilities of each heat exchanger type under the conditions inherent to HECTOR, thereby facilitating an informed selection for systems demanding high operational integrity and efficiency.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
NASA NTRS1975

Cross correlation anomaly detection system

This invention provides a method for automatically inspecting the surface of an object, such as an integrated circuit chip, whereby the data obtained by the light reflected from the surface, caused by a scanning light beam, is automatically compared with data representing acceptable values for each unique surface. A signal output provided indicated of acceptance or rejection of the chip. Acceptance is based on predetermined statistical confidence intervals calculated from known good regions of the object being tested, or their representative values. The method can utilize a known good chip, a photographic mask from which the I.C. was fabricated, or a computer stored replica of each pattern being tested.

Micka, E. Z.↗
NASA NTRS1994

Computing Misalignments From Measured Contact Resistances

Misalignments of contacts in integrated circuits computed, and measured contact resistances corrected for effects of misalignments by use of method based on relatively simple mathematical model of measured contact resistance. Flange resistance of aligned contact multiplied by semiempirical factor. Method particularly useful in estimating effects of misalignments on four- and six-terminal (Kelvin-tap) contact-resistance measurements taken with L-shaped test structures.

Lieneweg, Udo↗
NASA NTRS2007

A CMOS Imager with Focal Plane Compression using Predictive Coding

This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

Leon-Salas, Walter D.↗