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At least 613 records · Page 34

A Comparison of Three Programming Models for Adaptive Applications

We study the performance and programming effort for two major classes of adaptive applications under three leading parallel programming models. We find that all three models can achieve scalable performance on the state-of-the-art multiprocessor machines. The basic parallel algorithms needed for different programming models to deliver their best performance are similar, but the implementations differ greatly, far beyond the fact of using explicit messages versus implicit loads/stores. Compared with MPI and SHMEM, CC-SAS (cache-coherent shared address space) provides substantial ease of programming at the conceptual and program orchestration level, which often leads to the performance gain. However it may also suffer from the poor spatial locality of physically distributed shared data on large number of processors. Our CC-SAS implementation of the PARMETIS partitioner itself runs faster than in the other two programming models, and generates more balanced result for our application.

Shan, Hong-Zhang↗

Analysis and Optimization of Parallel Software Pipeline Performance

Pipelining is a common strategy for extracting parallelism from a collection of independent computational tasks, each of which is spread among a number of processors and has an implied data dependence. When implemented on MIMD parallel computers with finite process interrupt times, pipeline algorithms suffer from slowdown--in addition to the expected pipeline fill time--due to a wave-like propagation of delays. This phenomenon, which has been observed experimentally using the performance monitoring system AIMS, is investigated analytically, and an optimal correction is derived to eliminate the wave. Efficiency increase through the correction is verified experimentally.

VanderWijngaart, Rob F.↗

The Effect of Interrupts on Software Pipeline Execution on Message-Passing Architectures

Pipelining is a common strategy for extracting parallelism from a collection of independent computational tasks, each of which is spread among a number of processors and has an implied data dependence. When implemented on MIMD parallel computers with finite process interrupt times, pipeline algorithms suffer from slowdown--in addition to the expected pipeline fill time--due to a wave-like propagation of delays. This phenomenon, which has been observed experimentally using the performance monitoring system AIMS, is investigated analytically, and an optimal correction is derived to eliminate the wave. Efficiency increase through the correction is verified experimentally.

VanderWijngaart, Rob F.↗

Charon Toolkit for Parallel, Implicit Structured-Grid Computations: Functional Design

In a previous report the design concepts of Charon were presented. Charon is a toolkit that aids engineers in developing scientific programs for structured-grid applications to be run on MIMD parallel computers. It constitutes an augmentation of the general-purpose MPI-based message-passing layer, and provides the user with a hierarchy of tools for rapid prototyping and validation of parallel programs, and subsequent piecemeal performance tuning. Here we describe the implementation of the domain decomposition tools used for creating data distributions across sets of processors. We also present the hierarchy of parallelization tools that allows smooth translation of legacy code (or a serial design) into a parallel program. Along with the actual tool descriptions, we will present the considerations that led to the particular design choices. Many of these are motivated by the requirement that Charon must be useful within the traditional computational environments of Fortran 77 and C. Only the Fortran 77 syntax will be presented in this report.

VanderWijngaart, Rob F.↗

Real-time software receiver

A real-time software receiver that executes on a general purpose processor. The software receiver includes data acquisition and correlator modules that perform, in place of hardware correlation, baseband mixing and PRN code correlation using bit-wise parallelism.

Ledvina, Brent M.↗

Real-time software receiver

A real-time software receiver that executes on a general purpose processor. The software receiver includes data acquisition and correlator modules that perform, in place of hardware correlation, baseband mixing and PRN code correlation using bit-wise parallelism.

Ledvina, Brent M.↗

NASA Tech Briefs, March 2008

Topics covered include: WRATS Integrated Data Acquisition System; Breadboard Signal Processor for Arraying DSN Antennas; Digital Receiver Phase Meter; Split-Block Waveguide Polarization Twist for 220 to 325 GHz; Nano-Multiplication-Region Avalanche Photodiodes and Arrays; Tailored Asymmetry for Enhanced Coupling to WGM Resonators; Disabling CNT Electronic Devices by Use of Electron Beams; Conical Bearingless Motor/Generators; Integrated Force Method for Indeterminate Structures; Carbon-Nanotube-Based Electrodes for Biomedical Applications; Compact Directional Microwave Antenna for Localized Heating; Using Hyperspectral Imagery to Identify Turfgrass Stresses; Shaping Diffraction-Grating Grooves to Optimize Efficiency; Low-Light-Shift Cesium Fountain without Mechanical Shutters; Magnetic Compensation for Second-Order Doppler Shift in LITS; Nanostructures Exploit Hybrid-Polariton Resonances; Microfluidics, Chromatography, and Atomic-Force Microscopy; Model of Image Artifacts from Dust Particles; Pattern-Recognition System for Approaching a Known Target; Orchestrator Telemetry Processing Pipeline; Scheme for Quantum Computing Immune to Decoherence; Spin-Stabilized Microsatellites with Solar Concentrators; Phase Calibration of Antenna Arrays Aimed at Spacecraft; Ring Bus Architecture for a Solid-State Recorder; and Image Compression Algorithm Altered to Improve Stereo Ranging.

Source record↗

Partial Automation of Requirements Tracing

Requirements Tracing on Target (RETRO) is software for after-the-fact tracing of textual requirements to support independent verification and validation of software. RETRO applies one of three user-selectable information-retrieval techniques: (1) term frequency/inverse document frequency (TF/IDF) vector retrieval, (2) TF/IDF vector retrieval with simple thesaurus, or (3) keyword extraction. One component of RETRO is the graphical user interface (GUI) for use in initiating a requirements-tracing project (a pair of artifacts to be traced to each other, such as a requirements spec and a design spec). Once the artifacts have been specified and the IR technique chosen, another component constructs a representation of the artifact elements and stores it on disk. Next, the IR technique is used to produce a first list of candidate links (potential matches between the two artifact levels). This list, encoded in Extensible Markup Language (XML), is optionally processed by a filtering component designed to make the list somewhat smaller without sacrificing accuracy. Through the GUI, the user examines a number of links and returns decisions (yes, these are links; no, these are not links). Coded in XML, these decisions are provided to a "feedback processor" component that prepares the data for the next application of the IR technique. The feedback reduces the incidence of erroneous candidate links. Unlike related prior software, RETRO does not require the user to assign keywords, and automatically builds a document index.

Hayes, Jane↗

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As space missions continue to become more ambitious, complex, and distant to Earth, the need for advanced on-board intelligent decision making to guide everything from mission operations to fault detection and recovery has become a major front of space research. While the prevalence of research on such Artificial Intelligence / Machine Learning (AI/ML) modules has exploded, the capacity to experimentally validate such modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available AI/ML computational platforms via the TechEdSat (TES-n) flight series as part of what is programmatically referred to as the BRAINSTACK. BRAINSTACK will provide an orbital AI/ML evaluation laboratory where computational experiments are pre-loaded into memory prior to launch, and then executed as desired during the mission, with results reported back and program tweaks or new data sets uploaded as needed. Processors selected as part of the BRAINSTACK are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and more recently, neuromorphic processors in LEO operations. Neuromorphic processors are of particular interest due to their superior computational power efficiency over GPUs. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on January 13, 2022 and continues to operate in orbit despite almost no space environment modifications. The Intel Loihi Gen-1 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. This experiment utilized a Loihi packaged in the ‘Kapoho Bay’ USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by a host Intel Pentium single-board computer to handle scheduling of the AI/ML application payloads, and communications with the satellite vehicle manager. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the basis of the evolving BRAINSTACK in the upcoming three TES-n/NOW flights. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space AI/ML applications may be initially tested.

Artificial Intelligence↗

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As space missions continue to become more ambitious, complex, and distant to Earth, the need for advanced on-board intelligent decision making to guide everything from mission operations to fault detection and recovery has become a major front of space research. While the prevalence of research on such Artificial Intelligence / Machine Learning (AI/ML) modules has exploded, the capacity to experimentally validate such modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available AI/ML computational platforms via the TechEdSat (TES-n) flight series as part of what is programmatically referred to as the BRAINSTACK. BRAINSTACK will provide an orbital AI/ML evaluation laboratory where computational experiments are pre-loaded into memory prior to launch, and then executed as desired during the mission, with results reported back and program tweaks or new data sets uploaded as needed. Processors selected as part of the BRAINSTACK are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and more recently, neuromorphic processors in LEO operations. Neuromorphic processors are of particular interest due to their superior computational power efficiency over GPUs. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on January 13, 2022 and continues to operate in orbit despite almost no space environment modifications. The Intel Loihi Gen-1 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. This experiment utilized a Loihi packaged in the ‘Kapoho Bay’ USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by a host Intel Pentium single-board computer to handle scheduling of the AI/ML application payloads, and communications with the satellite vehicle manager. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the basis of the evolving BRAINSTACK in the upcoming three TES-n/NOW flights. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space AI/ML applications may be initially tested.

Artificial Intelligence↗

Implementation and performance of the Magellan digital correlator subsystem

The Magellan synthetic aperture radar (SAR) produces Venus surface images from data collected by the SAR carried on board the Magellan spacecraft. The core of the primary Magellan SAR processor is the digital correlator subsystem (DCS). The pipeline DSC architecture enables the Magellan primary SAR processor (PSP) to achieve real-time data processing capability. The implementation and performance of the DSC are described. Hardware (H/W) constraints that influenced the processing algorithm design are highlighted.

Chen, M.↗

Mark 3 correlator hardware and software

The Mark 3 correlator system is described in some detail. The correlator system is based on a modular philosophy. Each correlator module independently processes the data from one track pair. Therefore, 28 modules are necessary to complete a full one baseline processor and 84 modules for a full 3 baseline processor. Each correlator module has two interfaces: (1) data and clock from each of the two tracks to be correlated and (2) Computer Automated Measurement and Control (CAMAC) dataway interface to the computer. The processor is organized around the IEEE CAMAC standard architecture, housing 15 correlator modules in each of 6 crates. This allows one pass processing of a full 3 baseline 28 track observation or a 6 baseline (4 station) 14 track observation. The correlator architecture allows easy expansion for up to 8 stations. The computer system is an HP 1000 system utilizing a 16 bit minicomputer with disc and tape peripherals. The processing software is also organized in a modular fashion with many independent but cooperative programs controlling the operation of the Mark 3 processor. Processing time through the correlator is normally real time or faster, with graphics displays providing real time monitor and control of the processing operation.

Whitney, A. R.↗

TRAPEDS: Producing traces for multicomputers via execution-driven simulation

Trace-driven simulation is an important aid in performance analysis of computer systems. Capturing address traces for these simulations is a difficult problem for single processors and particularly for multicomputers. Even when existing trace methods can be used on multicomputers, the amount of collected data typically grows with the number of processors, so I/O and trace storage costs increase. A new technique is presented which modifies the executable code to dynamically collect the address trace from the user code and analyzes this trace during the execution of the program. This method helps resolve the I/O and storage problems and facilitates parallel analysis of the address trace. If a trace stored on disk is desired, the generated trace information can also be written to files during execution, with a resultant drop in program execution speed. An initial implementation on the Intel iPSC/2 hypercube multicomputer is detailed, and sample simulation results are presented. The effect of this trace collection method on execution time is illustrated.

Stunkel, Craig B.↗

TRAPEDS - Producing traces for multicomputers via execution driven simulation

Trace-driven simulation is an important aid in performance analysis of computer systems. Capturing address traces for these simulations is a difficult problem for single processors and particularly for multicomputers. Even when existing trace methods can be used on multicomputers, the amount of collected data typically grows with the number of processors, so I/O and trace storage costs increase. A new technique is presented which modifies the executable code to dynamically collect the address trace from the user code and analyzes this trace during the execution of the program. This method helps resolve the I/O and storage problems and facilitates parallel analysis of the address trace. If a trace stored on disk is desired, the generated trace information can also be written to files during execution, with a resultant drop in program execution speed. An initial implementation on the Intel iPSC/2 hypercube multicomputer is detailed, and sample simulation results are presented. The effect of this trace collection method on execution time is illustrated.

Stunkel, Craig B.↗

High Performance Morphological Filtering of Cirrus Emission from Infrared Images

The project was designed to explore new morphological filtering, techniques for the removal of foreground Galactic 'Cirrus' emission from NASA Infrared Astronomical Satellite (IRAS) data, especially at 100 microns, using parallel processors as the main engine for achieving this result. The ultimate aim was to provide NASA with completely filtered data by the end of the grant period for the entire IRAS 100 and possibly 60 micron database. If successful, the filtered data would reveal many new sources of IR emission, especially at low galactic latitudes, which had previously been heavily confused with diffuse Galactic 'cirrus'.

Appleton, P. N.↗

Robonaut 2 - Building a Robot on the International Space Station

In 2010, the Robonaut Project embarked on a multi‐phase mission to perform technology demonstrations on‐board the International Space Station (ISS), showcasing state of the art robotics technologies through the use of Robonaut 2 (R2). This phased approach implements a strategy that allows for the use of ISS as a test bed during early development to both demonstrate capability and test technology while still making advancements in the earth based laboratories for future testing and operations in space. While R2 was performing experimental trials onboard the ISS during the first phase, engineers were actively designing for Phase 2, Intra‐Vehicular Activity (IVA) Mobility, that utilizes a set of zero‐g climbing legs outfitted with grippers to grasp handrails and seat tracks. In addition to affixing the new climbing legs to the existing R2 torso, it became clear that upgrades to the torso to both physically accommodate the climbing legs and to expand processing power and capabilities of the robot were required. In addition to these upgrades, a new safety architecture was also implemented in order to account for the expanded capabilities of the robot. The IVA climbing legs not only needed to attach structurally to the R2 torso on ISS, but also required power and data connections that did not exist in the upper body. The climbing legs were outfitted with a blind mate adapter and coarse alignment guides for easy installation, but the upper body required extensive rewiring to accommodate the power and data connections. This was achieved by mounting a custom adapter plate to the torso and routing the additional wiring through the waist joint to connect to the new set of processors. In addition to the power and data channels, the integrated unit also required updated electronics boards, additional sensors and updated processors to accommodate a new operating system, software platform, and custom control system. In order to perform the unprecedented task of building a robot in space, extensive practice sessions and meticulous procedures were required. Since crew training time is at a premium, the R2 team took a skills‐based training approach to ensure the astronauts were proficient with a basic skill set while refining the detailed procedures over several practice sessions and simulations. In addition to the crew activities, meticulous ground procedures were required in order to upgrade firmware on the upper body motor drivers. The new firmware for the IVA mobility unit needed to be deployed using the old software system. This also provided an opportunity to upgrade the upper body joints with new software and allowed for limited insight into the success of the updates. Complete verification that the updated firmware was successfully loaded was not confirmed until the rewiring of the upper body torso was complete.

Diftler, Myron↗

A stored program channel processor for CAMAC

A PDP-15 interface was developed for the CAMAC instrumentation standard which implements the features of both the addressable I/0 bus and the single cycle data channel. The data channel section forms an independent I/0 processor which executes programs stored in core. Programs consist of CAMAC commands plus special control characters and commands.

Bercaw, R. W.↗