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Results for “SEMICONDUCTOR DEVICE”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 631 records · Page 35
All sourcesNASA NTRSDOE OSTI
NASA NTRS1979

Semiconductor structure

A technique for fabricating a semiconductor heterostructure by growth of a ternary semiconductor on a binary semiconductor substrate from a melt of the ternary semiconductor containing less than saturation of at least one common ingredient of both the binary and ternary semiconductors wherein in a single temperature step the binary semiconductor substrate is etched, a p-n junction with specific device characteristics is produced in the binary semiconductor substrate by diffusion of a dopant from the melt and a region of the ternary semiconductor of precise conductivity type and thickness is grown by virtue of a change in the melt characteristics when the etched binary semiconductor enters the melt.

Hovel, Harold J.↗
NASA NTRS2000

Method For Growth of Crystal Surfaces and Growth of Heteroepitaxial Single Crystal Films Thereon

A method of growing atomically-flat surfaces and high quality low-defect crystal films of semiconductor materials and fabricating improved devices thereon is discussed. The method is also suitable for growing films heteroepitaxially on substrates that are different than the film. The method is particularly suited for growth of elemental semiconductors (such as Si), compounds of Groups III and V elements of the Periodic Table (such as GaN), and compounds and alloys of Group IV elements of the Periodic Table (such as SiC).

Powell, J. Anthony↗
NASA NTRS2022

Mission Radiation Environment Modeling and Analysis: Avionics Trade Study for GCD Rad-Neuro Project

The two main objectives of this trade study are characterizing the mission radiation environment for multiple Design Reference Missions (DRM) and analysis of radiation effects on avionics with the goal of producing radiation tolerant Neuromorphic Computing processor chips with innovative radiation-induced fault mitigation. The NASA process for defining radiation requirements for flight avionics is applied to this domain. The effects of trapped protons and electrons in the Van Allen radiation belts predominates in Low-Earth-Orbit (LEO) and the solar wind, solar flares and Galactic Cosmic Rays (GCRs) are the dominant radiation challenge in the open space between the planets of our solar system. The nature and energy of the particles that cause circuit upset and failure is very different in the two regimes. Two results are produced from the radiation models: determining the Total Integrated Dose (TID) experienced by avionics for a given DRM and predicting the Single Event Effects (SEE) rates for avionics during high rate exposure. These tools are applied to existing semiconductors and can be used for predicting the radiation performance of future semiconductors based on early radiation testing of new devices.

Space Radiation↗
NASA NTRS2009

SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80 high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C

Patterson, Richard L.↗
NASA NTRS1994

A low cost igniter utilizing an SCB and titanium sub-hydride potassium perchlorate pyrotechnic

A conventional NSI (NASA Standard Initiator) normally employs a hot-wire ignition element to ignite ZPP (zirconium potassium perchlorate). With minor modifications to the interior of a header similar to an NSI device to accommodate an SCB (semiconductor bridge), a low cost initiator was obtained. In addition, the ZPP was replaced with THKP (titanium sub-hydride potassium perchlorate) to obtain increased overall gas production and reduced static-charge sensitivity. This paper reports on the all-fire and no-fire levels obtained and on a dual mix device that uses THKP as the igniter mix and a thermite as the output mix.

R. W. Bickes, Jr.↗
NASA NTRS1992

An overview of silicon carbide device technology

Recent progress in the development of silicon carbide (SiC) as a semiconductor is briefly reviewed. This material shows great promise towards providing electronic devices that can operate under the high-temperature, high-radiation, and/or high-power conditions where current semiconductor technologies fail. High quality single crystal wafers have become available, and techniques for growing high quality epilayers have been refined to the point where experimental SiC devices and circuits can be developed. The prototype diodes and transistors that have been produced to date show encouraging characteristics, but by the same token they also exhibit some device-related problems that are not unlike those faced in the early days of silicon technology development. Although these problems will not prevent the implementation of some useful circuits, the performance and operating regime of SiC electronics will be limited until these device-related issues are solved.

Neudeck, Philip G.↗
NASA NTRS2019

Characterization and Failure Analysis of 650 V Enhancement-Mode GaN HEMT for Cryogenically-Cooled Power Electronics

In order to evaluate the feasibility of newly developed GaN devices in a cryogenically-cooled converter, this paper characterizes a 650 V enhancement-mode Gallium-Nitride high-electron-mobility transistor (GaN HEMT) at cryogenic temperatures. The characterization includes both static and dynamic behaviors. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature (93 K) is 2.5 times higher than one at room temperature (298 K), and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the on-resistance of the channel at cryogenic temperature is only one-fifth of that at room temperature. The corresponding explanations of performance trends at cryogenic temperatures are also given from the view of semiconductor physics. In addition, several device failures were observed during the dynamic characterization of GaN HEMTs at cryogenic temperatures. The ultra-fast switching speed induced high di/dt and dv/dt at cryogenic temperatures amplifies the negative effects of parasitics inside the switching loop. Based on failure waveforms, two failure modes were classified, and detailed failure mechanisms caused by ultra-fast switching speed are given in this paper.

Static and dynamic characterization↗
NASA NTRS1989

Integrated Semiconductor/Optical Information Processors

Optical information processors made of integrated three-dimensional devices which include optical, electro-optical, and electronic devices. Integration achieved by combination and extension of advanced semiconductor (integrated-circuit) and integrated-optics technology. In integrated device, spatial light modulator fabricated on surface of chip. Leads to miniaturization of sophisticated optical information-processing systems.

Cheng, Li-Jen↗
NASA NTRS1981

Chemical composition of the SiO2/InSb interface as determined by X-ray photoelectron spectroscopy

In connection with the relatively poor insulating characteristics of the native oxides of most III-V compound semiconductors, there has been interest in the development of deposited dielectric layers for surface passivation and MOS device fabrication on III-V compound semiconductor substrates. The chemical system of SiO2 deposited on single-crystal InSb substrates has been proposed for the fabrication of IR CCD. The considered investigation is concerned with a detailed examination of the chemical nature of the interactions between deposited and native oxides using X-ray photoelectron spectroscopy (XPS) in conjunction with a chemical-etching technique for depth profiling. The compositional structure of the interfaces obtained in the SiO2/native oxide/InSb system is derived on the basis of an intensity analysis of XPS spectra. Thermal oxidation of the InSb substrate is found to result in an In-rich native oxide and excess elemental Sb at the native oxide/substrate interface.

Vasquez, R. P.↗
NASA NTRS1969

Radiation tolerant silicon nitride insulated gate field effect transistors

Metal-Insulated-Semiconductor Field Effect Transistor /MISFET/ device uses a silicon nitride passivation layer over a thin silicon oxide layer to enhance the radiation tolerance. It is useful in electronic systems exposed to space radiation environment or the effects of nuclear weapons.

Newman, P. A.↗
NASA NTRS1979

Semiconductor technology program. Progress briefs

The current status of NBS work on measurement technology for semiconductor materials, process control, and devices is reported. Results of both in-house and contract research are covered. Highlighted activities include modeling of diffusion processes, analysis of model spreading resistance data, and studies of resonance ionization spectroscopy, resistivity-dopant density relationships in p-type silicon, deep level measurements, photoresist sensitometry, random fault measurements, power MOSFET thermal characteristics, power transistor switching characteristics, and gross leak testing. New and selected on-going projects are described. Compilations of recent publications and publications in press are included.

Bullis, W. M.↗
NASA NTRS1980

Semiconductor technology program. Progress briefs

Measurement technology for semiconductor materials, process control, and devices is reviewed. Activities include: optical linewidth and thermal resistance measurements; device modeling; dopant density profiles; resonance ionization spectroscopy; and deep level measurements. Standardized oxide charge terminology is also described.

Bullis, W. M.↗
NASA NTRS1981

Time delay and integration detectors using charge transfer devices

An imaging system comprises a multi-channel matrix array of CCD devices wherein a number of sensor cells (pixels) in each channel are subdivided and operated in discrete intercoupled groups of subarrays with a readout CCD shift register terminating each end of the channels. Clock voltages, applied to the subarrays, selectively cause charge signal flow in each subarray in either direction independent of the other subarrays. By selective application of four phase clock voltages, either one, two or all three of the sections subarray sections cause charge signal flow in one direction, while the remainder cause charge signal flow in the opposite direction. This creates a form of selective electronic exposure control which provides an effective variable time delay and integration of three, six or nine sensor cells or integration stages. The device is constructed on a semiconductor sustrate with a buried channel and is adapted for front surface imaging through transparent doped tin oxide gates.

Mccann, D. H.↗
NASA NTRS1981

Semiconductor technology program: Progress briefs

Measurement technology for semiconductor materials, process control, and devices, is discussed. Silicon and silicon based devices are emphasized. Highlighted activities include semiinsulating GaAs characterization, an automatic scanning spectroscopic ellipsometer, linewidth measurement and coherence, bandgap narrowing effects in silicon, the evaluation of electrical linewidth uniformity, and arsenicomplanted profiles in silicon.

Galloway, K. F.↗
NASA NTRS1985

Integrated Laser and Light Detector

Proposed infrared optical transmitter tracks distant beacon and automatically point transmitted beam toward beacon. Essential transmitter is integrated gallium arsenide device containing electronically-steerable semiconductor injection laser and position detector that senses direction to beacon. With satisfactory optics and sufficient power, system used for long-distance transmission.

Katz, J.↗
NASA NTRS1986

Modelling short channel mosfets for use in VLSI

In an investigation of metal oxide semiconductor field effect transistor (MOFSET) devices, a one-dimensional mathematical model of device dynamics was prepared, from which an accurate and computationally efficient drain current expression could be derived for subsequent parameter extraction. While a critical review revealed weaknesses in existing 1-D models (Pao-Sah, Pierret-Shields, Brews, and Van de Wiele), this new model in contrast was found to allow all the charge distributions to be continuous, to retain the inversion layer structure, and to include the contribution of current from the pinched-off part of the device. The model allows the source and drain to operate in different regimes. Numerical algorithms used for the evaluation of surface potentials in the various models are presented.

Klafter, Alex↗
NASA NTRS1988

Materials for thermoelectric energy conversion

The field of thermoelectric energy conversion is reviewed from both a theoretical and an experimental standpoint. The basic theory is introduced and the thermodynamic and solid state views are compared. An overview of the development of thermoelectric materials is presented with particular emphasis being placed on the most recent developments in high-temperature semiconductors. A number of possible device applications are discussed and the successful use and suitability of these devices for space power is manifest.

Wood, C.↗
NASA NTRS1989

Variable-Energy Ion Beams For Modification Of Surfaces

Beam of low-energy negative oxygen ions used to grow layer of silicon dioxide on silicon. Beam unique both in purity, contains no molecular oxygen or other charged species, and in low energy, which is insufficient to damage silicon by physically displacing atoms. Low-energy growth accomplished with help of ion-beam apparatus. Directs electrons into crosswise stream of gas, generating stream of negative ions. Pair of charged plates separates ions from accompanying electrons and diverts ion beam to target - silicon substrate. Diameter of beam at target 0.5 to 0.75 cm. Promises useful device to study oxidation of semiconductors and, in certain applications, to replace conventional oxidation processes.

Chutjian, Ara↗