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At least 73 records · Page 4

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NASA NTRS1987

High data rate Reed-Solomon encoding and decoding using VLSI technology

Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

Miller, Warner↗

NASA NTRS1989

Wiring Viterbi decoders (splitting deBruijn graphs)

A new Viterbi decoder, capable of decoding convolutional codes with constraint lengths up to 15, is under development for the Deep Space Network (DSN). A key feature of this decoder is a two-level partitioning of the Viterbi state diagram into identical subgraphs. The larger subgraphs correspond to circuit boards, while the smaller subgraphs correspond to Very Large Scale Integration (VLSI) chips. The full decoder is built from identical boards, which in turn are built from identical chips. The resulting system is modular and hierarchical. The decoder is easy to implement, test, and repair because it uses a single VLSI chip design and a single board design. The partitioning is completely general in the sense that an appropriate number of boards or chips may be wired together to implement a Viterbi decoder of any size greater than or equal to the size of the module.

Collins, O.↗

NASA NTRS1988

Decoding techniques for fine-fine geometry multi-anode microchannel arrays

The Multi-Anode Microchannel Array (MAMA) is a photon-counting detector which decodes the position of an event through coincidence discrimination. The decoding algorithm which associates a given event with the appropriate pixel is determined by the geometry of the array. The decoding process can be divided into two tasks: anode encoding and pixel decoding. Techniques for performing both tasks are described and contrasted in light of application requirements. Decode times of 75 nanoseconds have been achieved, and considerably faster decoders are possible given new architectures and technologies.

Kasle, David B.↗

NASA NTRS1991

Testing interconnected VLSI circuits in the Big Viterbi Decoder

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.↗

NASA NTRS1996

Good trellises for IC implementation of viterbi decoders for linear block codes

This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Moorthy, H. T.↗

NASA NTRS1996

Good trellises for IC implementation of viterbi decoders for linear block codes

Lin, Shu↗

NASA NTRS1997

Good Trellises for IC Implementation of Viterbi Decoders for Linear Block Codes

This paper investigates trellis structures of linear block codes for the integrated circuit (IC) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper-bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called add-compare-select (ACS)-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the very large scale integration (VISI) complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a nonminimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Moorthy, Hari T.↗

NASA NTRS2004

Milcom 04 Paper ID# 1158: A New Class of Turbo-like Codes with Efficient and Practical High-speed Decoders

Turbo codes not only achieve near Shannon-capacity performance, but also have decoders with modest complexity, which is crucial for implementation. So far efficient architectures for decoding of turbo codes have been proposed that is suitable for serial processing. In this paper a novel architecture for very high-speed turbo decoder is presented. The performance of this decoder is illustrated and the tradeoff between speed and efficiency is discussed. It is shown that some decoders can run faster by some order of magnitude while maintaining almost the same processing load.

interleaver design↗

NASA NTRS1971

Viterbi decoding for satellite and space communication.

Convolutional coding and Viterbi decoding, along with binary phase-shift keyed modulation, is presented as an efficient system for reliable communication on power limited satellite and space channels. Performance results, obtained theoretically and through computer simulation, are given for optimum short constraint length codes for a range of code constraint lengths and code rates. System efficiency is compared for hard receiver quantization and 4 and 8 level soft quantization. The effects on performance of varying of certain parameters relevant to decoder complexity and cost are examined. Quantitative performance degradation due to imperfect carrier phase coherence is evaluated and compared to that of an uncoded system. As an example of decoder performance versus complexity, a recently implemented 2-Mbit/sec constraint length 7 Viterbi decoder is discussed. Finally a comparison is made between Viterbi and sequential decoding in terms of suitability to various system requirements.

Heller, J. A.↗

NASA NTRS1972

A very high speed hard decision sequential decoder.

Description of a 40-megabit-per-second hard decision sequential decoder which employs the fastest commercially available digital integrated circuits - MECL III. With this decoder an internal computational rate of 70,000,000 computations per second has been achieved. The computational efficiency of the decoding algorithm has been improved by incorporating two modifications to the Fano algorithm - namely, 'double quick threshold loosening' and 'diagonal steps.' On the basis of preliminary results, an output error rate of 0.00001 can be achieved with E sub b/N sub zero less than 5.4 dB at data rates up to 40 megabits per second. The very high internal operating speed of the decoder represents a factor of five increase in speed over any previous sequential decoder.

Gilhousen, K. S.↗

NASA NTRS1972

A very high speed hard decision sequential decoder.

Description of a 40-Mbps hard-decision sequential decoder for high-data-rate coding systems for earth-orbiting space missions with power-limited links. A prototype decoder has been designed and fabricated using the fastest commercially available digital integrated circuits, MECL III. Thus far, an internal computational rate of 70 million computations per second has been achieved. Computational efficiency of the decoding algorithm was greatly improved by incorporating two modifications to the Fano algorithm - 'double quick threshold loosening' and 'diagonal steps.' Preliminary results indicate that an output error rate of 0.00001 can be achieved with E sub b/N sub zero less than 5.4 dB at data rates up to 40 Mbps. At lower data rates, even less signal energy is required. This decoder is believed to be at least five times faster than any previous sequential decoder.

Gilhousen, K. S.↗

NASA NTRS1973

On the error probability of general tree and trellis codes with applications to sequential decoding

An upper bound on the average error probability for maximum-likelihood decoding of the ensemble of random binary tree codes is derived and shown to be independent of the length of the tree. An upper bound on the average error probability for maximum-likelihood decoding of the ensemble of random L-branch binary trellis codes of rate R = 1/n is derived which separates the effects of the tail length T and the memory length M of the code. It is shown that the bound is independent of the length L of the information sequence. This implication is investigated by computer simulations of sequential decoding utilizing the stack algorithm. These simulations confirm the implication and further suggest an empirical formula for the true undetected decoding error probability with sequential decoding.

Johannesson, R.↗

NASA NTRS1976

A new sequential decoder for the DSN telemetry subsystem

A sequential decoder was implemented in the DSS telemetry subsystem for the DSN MARK 3 data system implementation. This decoder performs the same decoding function as the data decoder assembly performs in the telemetry and command data handling subsystem. However, the new decoder is much faster, allowing potentially high data rates in the future.

Wilcher, J. H.↗

NASA NTRS1976

The fast decoding of Reed-Solomon codes using number theoretic transforms

It is shown that Reed-Solomon (RS) codes can be encoded and decoded by using a fast Fourier transform (FFT) algorithm over finite fields. The arithmetic utilized to perform these transforms requires only integer additions, circular shifts and a minimum number of integer multiplications. The computing time of this transform encoder-decoder for RS codes is less than the time of the standard method for RS codes. More generally, the field GF(q) is also considered, where q is a prime of the form K x 2 to the nth power + 1 and K and n are integers. GF(q) can be used to decode very long RS codes by an efficient FFT algorithm with an improvement in the number of symbols. It is shown that a radix-8 FFT algorithm over GF(q squared) can be utilized to encode and decode very long RS codes with a large number of symbols. For eight symbols in GF(q squared), this transform over GF(q squared) can be made simpler than any other known number theoretic transform with a similar capability. Of special interest is the decoding of a 16-tuple RS code with four errors.

Reed, I. S.↗

NASA NTRS1979

On the distribution of computation for sequential decoding using the stack algorithm

A method is developed for estimating the computational distribution for the stack algorithm for sequential decoding, that is, the probability that the computation required to decode the first branch of the tree is greater than or equal to N, for small N. The analysis relies heavily on the theory of multitype branching processes. A step in the analysis is the determination of the distribution of the minimum of the cumulative metrics along the transmitted path in the code tree. This is used to obtain the distribution of the number of computations made by the decoder in order to decode the first branch in the tree, and this random variable serves as an approximation of the average number of computations per decoded branch. At information rates below the cutoff rate, the calculated computational performance is virtually identical to that obtained by time-consuming simulations.

Johannesson, R.↗

NASA NTRS1983

Symbol synchronization for the TDRSS decoder

Each 8 bits out of the Viterbi decoder correspond to one symbol of the R/S code. Synchronization must be maintained here so that each 8-bit symbol delivered to the R/S decoder corresponds to an 8-bit symbol from the R/S encoder. Lack of synchronization, would cause an error in almost every R/S symbol since even a - 1-bit sync slip shifts every bit in each 8-bit symbol by one position, therby confusing the mapping betweeen 8-bit sequences and symbols. The error correcting capability of the R/S code would be exceeded. Possible ways to correcting this condition include: (1) designing the R/S decoder to recognize the overload and shifting the output sequence of the inner decoder to establish a different sync state; (2) using the characteristics of the inner decoder to establish symbol synchronization for the outer code, with or without a deinterleaver and an interleaver; and (3) modifying the encoder to alternate periodically between two sets of generators.

Costello, D. J., Jr.↗

NASA NTRS1983

Decoders for MST radars

Decoding techniques and equipment used by MST radars are described and some recommendations for new systems are presented. Decoding can be done either by software in special-purpose (array processors, etc.) or general-purpose computers or in specially designed digital decoders. Both software and hardware decoders are discussed and the special case of decoding for bistatic radars is examined.

Woodman, R. F.↗

NASA NTRS1986

Modular VLSI Reed-Solomon Decoder

Proposed Reed-Solomon (RS) decoder assembled from very-large-scale integrated-circuit (VLSI) building blocks. Decoder exploits recursive forms in RS decoding algorithms. RS codes capable of correcting random or burst errors in telemetry and other data-communication signals. Because of small size and low power consumption, advantageous to employ several such decoders in parallel-processing scheme to increase decoding speed.

Liu, K. Y.↗