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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS2006

X-Ray Detector Research at MSFC for Space Applications

NASA's Vision for Space Exploration has specific goals aimed at exploring the Solar System. This vision, under presidential mandate includes landing humans on the moon before the end of the next decade, paving the way for eventual journeys to Mars and beyond. The first missions to the moon will be in the form of both Orbiters and Landers, with the goal of paving the way for human return. One of the instruments we are currently working on,in collaboration with Brookhaven National Laboratory, is a lunar orbiter fluorescent x-ray spectrometer to finely map the light elements (down to Carbon) on surface of the moon. Funded NASA s Planetary Instrument Definition and Development Program the instrument is based on silicon drift detector arrays read out by custom ASICs. These offer the promise of high spectral resolution, necessary for resolving weak lines against a strong background continuum, and very low power requirements, necessary for large areas (greater than 500 square centimeters) required for future lunar missions. Further, the inherent radiation hardness of these detectors makes them ideal candidates for exploring the Jovian system, where the harsh radiation environment from Jupiter s radiation belts creates unfavorable detector conditions. Looking beyond our solar system, in the hard x-ray regime (20-80keV.), we are studying Cadmium-Zinc-Telluride pixilated detectors as feasible candidates for focal plane detectors of a hard x-ray telescope. This energy region bridges the gap between thermal and non-thermal x-ray emission from astronomical sources, will allow us to better understand supernovae nucleosynthesis (such as through the Ti-44 lines at 68keV and 78keV), Active Galactic Nuclei and other compact objects, more completely. The detectors that we are characterizing are 2mm in thickness and are pixilated with a 16x16 array of 300 micrometer pitch pixels (50micometer gap). These detectors are designed at Rutherford Appleton Laboratory, material is from eV Products, and polymer flip-chip assembly was performed by a commercial vendor. An energy resolution of 2.0% at 60keV (or better) should allow us to sufficiently distinguish lines of interest from background continuum, and the detector spatial resolution should be fine enough to over-sample the focal spot from the x-ray focusing optics by about a factor of two. Full technical details of these developments will be presented.

Gaskin, Jessica↗
NASA NTRS2004

Qualification and Reliability for MEMS and IC Packages

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

inertial measurement unit↗
NASA NTRS2007

Automated Hybridization of X-ray Absorber Elements-A Path to Large Format Microcalorimeter Arrays

In the design of microcalorimeters, it is often desirable to produce the X-ray absorber separately from the detector element. In this case, the attachment of the absorber to the detector element with the required thermal and mechanical characteristics is a major challenge. In such arrays, the attachment has been done by hand. This process is not easily extended to the large format arrays required for future X- ray astronomy missions such as the New x-ray Telescope or NeXT. In this paper we present an automated process for attaching absorber tiles to the surface of a large-scale X-ray detector array. The absorbers are attached with stycast epoxy to a thermally isolating polymer structure made of SU-8. SU-8 is a negative epoxy based photo resist produced by Microchem. We describe the fabrication of the X-ray absorbers and their suspension on a handle die in an adhesive matrix. We describe the production process for the polymer isolators on the detector elements. We have developed a new process for the alignment, and simultaneous bonding of the absorber tiles to an entire detector array. This process uses equipment and techniques used in the flip-chip bonding industry and approaches developed in the fabrication of the XRS-2 instrument. XRS-2 was an X-ray spectrometer that was launched on the Suzaku telescope in July 10, 2005. We describe the process and show examples of sample arrays produced by this process. Arrays with up to 300 elements have been bonded. The present tests have used dummy absorbers made of Si. In future work, we will demonstrate bonding of HgTe absorbers.

Moseley, S.↗
NASA NTRS1986

PbS-PbSe IR detector arrays

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chipping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Barrett, John R.↗
NASA NTRS2007

Automated Absorber Attachment for X-ray Microcalorimeter Arrays

Our goal is to develop a method for the automated attachment of large numbers of absorber tiles to large format detector arrays. This development includes the fabrication of high quality, closely spaced HgTe absorber tiles that are properly positioned for pick-and-place by our FC150 flip chip bonder. The FC150 also transfers the appropriate minute amount of epoxy to the detectors for permanent attachment of the absorbers. The success of this development will replace an arduous, risky and highly manual task with a reliable, high-precision automated process.

Moseley, S.↗
NASA NTRS2008

MEMS Microshutter Array System for James Webb Space Telescope

A complex MEMS microshutter array system has been developed at NASA Goddard Space Flight Center (GSFC) for use as a multi-object aperture array for a Near-Infrared Spectrometer (NIRSpec). The NIRSpec is one of the four major instruments carried by the James Webb Space Telescope (JWST), the next generation of space telescope after the Hubble Space Telescope retires. The microshutter arrays (MSAs) are designed for the selective transmission of light with high efficiency and high contrast. It is demonstrated in Figure 1 how a MSA is used as a multiple object selector in deep space. The MSAs empower the NIRSpec instrument simultaneously collect spectra from more than 100 targets therefore increases the instrument efficiency 100 times or more. The MSA assembly is one of three major innovations on JWST and the first major MEMS devices serving observation missions in space. The MSA system developed at NASA GSFC is assembled with four quadrant fully addressable 365x171 shutter arrays that are actuated magnetically, latched and addressed electrostatically. As shown in Figure 2, each MSA is fabricated out of a 4' silicon-on-insulator (SOI) wafer using MEMS bulk-micromachining technology. Individual shutters are close-packed silicon nitride membranes with a pixel size close to 100x200 pm (Figure 3). Shutters are patterned with a torsion flexure permitting shutters to open 90 degrees with a minimized mechanical stress concentration. In order to prevent light leak, light shields are made on to the surrounding frame of each shutter to cover the gaps between the shutters and the Game (Figure 4). Micro-ribs and sub-micron bumps are tailored on hack walls and light shields, respectively, to prevent sticktion, shown in Figures 4 and 5. JWST instruments are required to operate at cryogenic temperatures as low as 35K, though they are to be subjected to various levels of ground tests at room temperature. The shutters should therefore maintain nearly flat in the entire temperature range between 35K and 300K. Through intensive numerical simulations and experimental studies, an optically opaque and electrically conductive metal-nitride thin film was selected as a coating material deposited on the shutters with the best thermal-expansion match to silicon nitride - the shutter blade thin film material. A shutter image shown in Figure 6 was taken at room temperature, presenting shutters slightly bowing down as expected. Shutters become flat when the temperature decreases to 35K. The MSAs are then bonded to silicon substrates that are fabricated out of 6" single-silicon wafers in the thickness of 2mm. The bonding is conducted using a novel single-sided indium flip-chip bonding technology. Indium bumps fabricated on a substrate are shown in Figure 7. There are 180,000 indium bumps for bonding a flight format MSA array to its substrate. Besides a MSA, each substrate houses five customer-designed ASIC (Application Specific Integrated Circuit) multiplexer/address chips for 2-dimensional addressing, twenty capacitors, two temperature sensors, numbers of resistors and all necessary interconnects, as shown in Figure 8. Complete MSA quadrant assemblies have been successfully manufactured and fully functionally tested. The assemblies have passed a series of critical reviews required by JWST in satisfying all the design specifications. The qualification tests cover programmable 2-D addressing, life tests, optical contrast tests, and environmental tests including radiation, vibration, and acoustic tests. A 2-D addressing pattern with 'ESA' letters programmed in a MSA is shown in Figure 9. The MSAs passed 1 million cycle life tests and achieved high optical contrast over 10,000. MSA teams are now making progress in final fabrication, testing and assembly (Figure 10). The delivery of flight-format MSA system is scheduled at the end of 2008 for being integrated to the focal plane of the NIRSpec detectors.

Li, Mary J.↗
NASA NTRS2009

100-GHz Phase Switch/Mixer Containing a Slot-Line Transition

A circuit that can function as a phase switch, frequency mixer, or frequency multiplier operates over a broad frequency range in the vicinity of 100 GHz. Among the most notable features of this circuit is a grounded uniplanar transition (in effect, a balun) between a slot line and one of two coplanar waveguides (CPWs). The design of this circuit is well suited to integration of the circuit into a microwave monolithic integrated circuit (MMIC) package. One CPW is located at the input end and one at the output end of the top side of a substrate on which the circuit is fabricated (see Figure 1). The input CPW feeds the input signal to antiparallel flip-chip Schottky diodes connected to the edges of the slot line. Phase switching is effected by the combination of (1) the abrupt transition from the input CPW to the slot line and (2) CPW ground tuning effected by switching of the bias on the diodes. Grounding of the slot metal to the bottom metal gives rise to a frequency cutoff in the slot. This cutoff is valuable for separating different frequency components when the circuit is used as a mixer or multiplier. Proceeding along the slot line toward the output end, one encounters the aforementioned transition, which couples the slot line to the output CPW. Impedance tuning of the transition is accomplished by use of a high-impedance section immediately before the transition.

Gaier, Todd↗
NASA NTRS2009

Two-Step Plasma Process for Cleaning Indium Bonding Bumps

A two-step plasma process has been developed as a means of removing surface oxide layers from indium bumps used in flip-chip hybridization (bump bonding) of integrated circuits. The two-step plasma process makes it possible to remove surface indium oxide, without incurring the adverse effects of the acid etching process.

Greer, Harold F.↗
NASA NTRS2010

NASA Tech Briefs, September 2010

Topics covered include: Instrument for Measuring Thermal Conductivity of Materials at Low Temperatures; Multi-Axis Accelerometer Calibration System; Pupil Alignment Measuring Technique and Alignment Reference for Instruments or Optical Systems; Autonomous System for Monitoring the Integrity of Composite Fan Housings; A Safe, Self-Calibrating, Wireless System for Measuring Volume of Any Fuel at Non-Horizontal Orientation; Adaptation of the Camera Link Interface for Flight-Instrument Applications; High-Performance CCSDS Encapsulation Service Implementation in FPGA; High-Performance CCSDS AOS Protocol Implementation in FPGA; Advanced Flip Chips in Extreme Temperature Environments; Diffuse-Illumination Systems for Growing Plants; Microwave Plasma Hydrogen Recovery System; Producing Hydrogen by Plasma Pyrolysis of Methane; Self-Deployable Membrane Structures; Reactivation of a Tin-Oxide-Containing Catalys; Functionalization of Single-Wall Carbon Nanotubes by Photo-Oxidation; Miniature Piezoelectric Macro-Mass Balance; Acoustic Liner for Turbomachinery Applications; Metering Gas Strut for Separating Rocket Stages; Large-Flow-Area Flow-Selective Liquid/Gas Separator; Counterflowing Jet Subsystem Design; Water Tank with Capillary Air/Liquid Separation; True Shear Parallel Plate Viscometer; Focusing Diffraction Grating Element with Aberration Control; Universal Millimeter-Wave Radar Front End; Mode Selection for a Single-Frequency Fiber Laser; Qualification and Selection of Flight Diode Lasers for Space Applications; Plenoptic Imager for Automated Surface Navigation; Maglev Facility for Simulating Variable Gravity; Hybrid AlGaN-SiC Avalanche Photodiode for Deep-UV Photon Detection; High-Speed Operation of Interband Cascade Lasers; 3D GeoWall Analysis System for Shuttle External Tank Foreign Object Debris Events; Charge-Spot Model for Electrostatic Forces in Simulation of Fine Particulates; Hidden Statistics Approach to Quantum Simulations; Reconstituted Three-Dimensional Interactive Imaging; Determining Atmospheric-Density Profile of Titan; Digital Microfluidics Sample Analyzer; Radiation Protection Using Carbon Nanotube Derivatives; Process to Selectively Distinguish Viable from Non-Viable Bacterial Cells; and TEAMS Model Analyzer.

Source record↗
NASA NTRS2010

New Technology for Microfabrication and Testing of a Thermoelectric Device for Generating Mobile Electrical Power

We report the results of fabrication and testing of a thermoelectric power generation module. The module was fabricated using a new "flip-chip" module assembly technique that is scalable and modular. This technique results in a low value of contact resistivity ( < or = 10(exp 5) Ohms-sq cm). It can be used to leverage new advances in thin-film and nanostructured materials for the fabrication of new miniature thermoelectric devices. It may also enable monolithic integration of large devices or tandem arrays of devices on flexible or curved surfaces. Under mild testing, a power of 22 mW/sq cm was obtained from small (<100 K) temperature differences. At higher, more realistic temperature differences, approx.500 K, where the efficiency of these materials greatly improves, this power density would scale to between 0.5 and 1 Watt/cm2. These results highlight the excellent potential for the generation and scavenging of electrical power of practical and usable magnitude for remote applications using thermoelectric power generation technologies.

Prasad, Narashimha S.↗
NASA NTRS2004

AIN-Based Packaging for SiC High-Temperature Electronics

Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

Savrun, Ender↗
NASA NTRS2011

NASA Tech Briefs, May 2011

Topics covered include: 1) Method to Estimate the Dissolved Air Content in Hydraulic Fluid; 2) Method for Measuring Collimator-Pointing Sensitivity to Temperature Changes; 3) High-Temperature Thermometer Using Cr-Doped GdAlO3 Broadband Luminescence; 4)Metrology Arrangement for Measuring the Positions of Mirrors of a Submillimeter Telescope; 5) On-Wafer S-Parameter Measurements in the 325-508-GHz Band; 6) Reconfigurable Microwave Phase Delay Element for Frequency Reference and Phase-Shifter Applications; 7) High-Speed Isolation Board for Flight Hardware Testing; 8) High-Throughput, Adaptive FFT Architecture for FPGA-Based Spaceborne Data Processors; 9) 3D Orbit Visualization for Earth-Observing Missions; 10) MaROS: Web Visualization of Mars Orbiting and Landed Assets; 11) RAPID: Collaborative Commanding and Monitoring of Lunar Assets; 12) Image Segmentation, Registration, Compression, and Matching; 13) Image Calibration; 14) Rapid ISS Power Availability Simulator; 15) A Method of Strengthening Composite/Metal Joints; 16) Pre-Finishing of SiC for Optical Applications; 17) Optimization of Indium Bump Morphology for Improved Flip Chip Devices; 18) Measuring Moisture Levels in Graphite Epoxy Composite Sandwich Structures; 19) Marshall Convergent Spray Formulation Improvement for High Temperatures; 20) Real-Time Deposition Monitor for Ultrathin Conductive Films; 21) Optimized Li-Ion Electrolytes Containing Triphenyl Phosphate as a Flame-Retardant Additive; 22) Radiation-Resistant Hybrid Lotus Effect for Achieving Photoelectrocatalytic Self-Cleaning Anticontamination Coatings; 23) Improved, Low-Stress Economical Submerged Pipeline; 24) Optical Fiber Array Assemblies for Space Flight on the Lunar Reconnaissance Orbiter; 25) Local Leak Detection and Health Monitoring of Pressurized Tanks; 26) Dielectric Covered Planar Antennas at Submillimeter Wavelengths for Terahertz Imaging; 27) Automated Cryocooler Monitor and Control System; 28) Broadband Achromatic Phase Shifter for a Nulling Interferometer; 29) Super Dwarf Wheat for Growth in Confined Spaces; 30) Fine Guidance Sensing for Coronagraphic Observatories; 31) Single-Antenna Temperature- and Humidity-Sounding Microwave Receiver; 32) Multi-Wavelength, Multi-Beam, and Polarization-Sensitive Laser Transmitter for Surface Mapping; 33) Optical Communications Link to Airborne Transceiver; 34) Ascent Heating Thermal Analysis on Spacecraft Adaptor Fairings; 35) Entanglement in Self-Supervised Dynamics; 36) Prioritized LT Codes; 37) Fast Image Texture Classification Using Decision Trees; 38) Constraint Embedding Technique for Multibody System Dynamics; 39) Improved Systematic Pointing Error Model for the DSN Antennas; 40) Observability and Estimation of Distributed Space Systems via Local Information-Exchange Networks; 41) More-Accurate Model of Flows in Rocket Injectors; 42) In-Orbit Instrument-Pointing Calibration Using the Moon as a Target; 43) Reliability of Ceramic Column Grid Array Interconnect Packages Under Extreme Temperatures; 44) Six Degrees-of-Freedom Ascent Control for Small-Body Touch and Go; and 45) Optical-Path-Difference Linear Mechanism for the Panchromatic Fourier Transform Spectrometer.

Source record↗
NASA NTRS2012

Method to Improve Indium Bump Bonding via Indium Oxide Removal Using a Multi-Step Plasma Process

A process for removing indium oxide from indium bumps in a flip-chip structure to reduce contact resistance, by a multi-step plasma treatment. A first plasma treatment of the indium bumps with an argon, methane and hydrogen plasma reduces indium oxide, and a second plasma treatment with an argon and hydrogen plasma removes residual organics. The multi-step plasma process for removing indium oxide from the indium bumps is more effective in reducing the oxide, and yet does not require the use of halogens, does not change the bump morphology, does not attack the bond pad material or under-bump metallization layers, and creates no new mechanisms for open circuits.

Greer, H. Frank↗
NASA NTRS2012

High Energy/LET Radiation EEE Parts Certification Handbook

Certifying electronic components is a very involved process. It includes pre-coordination with the radiation test facility for time, schedule and cost, as well as intimate work with designers to develop test procedures and hardware. It also involves work with radiation engineers to understand the effects of the radiation field on the test article/setup as well as the analysis and production of a test report. The technical content of traditional ionizing radiation testing protocol is in wide use and generally follows established standards (ref. Appendix C). This document is not intended to cover all these areas but to cover the methodology of using Variable Depth Bragg Peak (VDBP) to accomplish the goal of characterizing an electronic component. The Variable Depth Bragg Peak (VDBP) test method is primarily used for deep space applications of electronics. However, it can be used on any part for any radiation environment, especially those parts where the sensitive volume cannot be reached by the radiation beam. An example of this problem would be issues that arise in de-lidding of parts or in parts with flip-chip designs, etc. The VDBP method is ideally suited to test modern avionics designs which increasingly incorporate commercial off-the-shelf (COTS) parts and units. Johnson Space Center (JSC) developed software provides assistance to users in developing the radiation characterization data from the raw test data.

Reddell, Brandon↗
NASA NTRS2012

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

The Cosmology Large Angular Scale Surveyor (CLASS) is a ground-based instrument that will measure the polarization of the cosmic microwave background to search for evidence for gravitational waves from a posited epoch of inflation early in the Universe s history. This measurement will require integration of superconducting transition-edge sensors with microwave waveguide inputs with excellent control of systematic errors, such as unwanted coupling to stray signals at frequencies outside of a precisely defined microwave band. To address these needs we present work on the fabrication of micromachined silicon, producing conductive quarter-wave backshort assemblies for the CLASS 40 GHz focal plane. Each 40 GHz backshort assembly consists of three degeneratively doped silicon wafers. Two spacer wafers are micromachined with through-wafer vias to provide a 2.04 mm long square waveguide delay section. The third wafer terminates the waveguide delay in a short. The three wafers are bonded at the wafer level by Au-Au thermal compression bonding then aligned and flip chip bonded to the CLASS detector at the chip level. The micromachining techniques used have been optimized to create high aspect ratio waveguides, silicon pillars, and relief trenches with the goal of providing improved out of band signal rejection. We will discuss the fabrication of integrated CLASS superconducting detector chips with the quarter-wave backshort assemblies.

Crowe, Erik J.↗
NASA NTRS2012

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

The Cosmology Large Angular Scale Surveyor (CLASS) is a ground-based instrument that will measure the polarization of the cosmic microqave background to search for gravitational waves form a posited epoch of inflation early in the universe's history. This measurement will require integration of superconducting transition-edge sensors with microwave waveguide inputs with good conrol of systematic errors, such as unwanted coupling to stray signals at frequencies outside of a precisely defined microwave band. To address these needs we will present work on the fabrication of silicon quarter-wave backshorts for the CLASS 40GHz focal plane. The 40GHz backshort consists of three degeneratively doped silicon wafers. Two spacer wafers are micromachined with through wafer vins to provide a 2.0mm long square waveguide. The third wafer acts as the backshort cap. The three wafers are bonded at the wafer level by Au-Au thermal compression bonding then aligned and flip chip bonded to the CLASS detector at the chip level. The micromachining techniques used have been optimized to create high aspect ratio waveguides, silicon pillars, and relief trenches with the goal of providing improved out of band signal rejection. We will discuss the fabrication of integrated CLASS superconducting detectors with silicon quarter wave backshorts and present current measurement results.

Crowe, Erik J.↗
NASA NTRS2013

Broad Frequency LTCC Vertical Interconnect Transition for Multichip Modules and System on Package Applications

Various stripline structures and flip chip interconnect designs for high-speed digital communication systems implemented in low temperature co-fired ceramic (LTCC) substrates are studied in this paper. Specifically, two different transition designs from edge launch 2.4 millimeter connectors to stripline transmission lines embedded in LTCC are discussed. After characterizing the DuPont (sup trademark) 9K7 green tape, different designs are proposed to improve signal integrity for high-speed digital data. The full-wave simulations and experimental data validate the presented designs over a broad frequency band from Direct Current to 50 gigahertz and beyond.

Full-tape-thickness feature; LTCC 9K7 interconnect↗
NASA NTRS2019

Proton Testing of nVidia Jetson TX2

Single-Event Effects (SEE) testing was conducted on the nVidia Jetson TX2 System on Chip (SOC). Testing was conducted at Massachusetts General Hospital's (MGH) Francis H. Burr Proton Therapy Center on June 2nd, 2019.

System on Chip (SOC)↗