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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1984

MOSFET and MOS capacitor responses to ionizing radiation

The ionizing radiation responses of metal oxide semiconductor (MOS) field-effect transistors (FETs) and MOS capacitors are compared. It is shown that the radiation-induced threshold voltage shift correlates closely with the shift in the MOS capacitor inversion voltage. The radiation-induced interface-state density of the MOSFETs and MOS capacitors was determined by several techniques. It is shown that the presence of 'slow' states can interfere with the interface-state measurements.

Benedetto, J. M.↗
DOE OSTI2023

Towards Low-Temperature CVD Synthesis and Characterization of Mono- or Few-Layer Molybdenum Disulfide

Molybdenum disulfide (MoS 2 ) transistors are a promising alternative for the semiconductor industry due to their large on/off current ratio (>10 10 ), immunity to short-channel effects, and unique switching characteristics. MoS 2 has drawn considerable interest due to its intriguing electrical, optical, sensing, and catalytic properties. Monolayer MoS 2 is a semiconducting material with a direct band gap of ~1.9 eV, which can be tuned. Commercially, the aim of synthesizing a novel material is to grow high-quality samples over a large area and at a low cost. Although chemical vapor deposition (CVD) growth techniques are associated with a low-cost pathway and large-area material growth, a drawback concerns meeting the high crystalline quality required for nanoelectronic and optoelectronic applications. This research presents a lower-temperature CVD for the repeatable synthesis of large-size mono- or few-layer MoS 2 using the direct vapor phase sulfurization of MoO 3 . The samples grown on Si/SiO 2 substrates demonstrate a uniform single-crystalline quality in Raman spectroscopy, photoluminescence (PL), scanning electron microscopy (SEM), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and scanning transmission electron microscopy. These characterization techniques were targeted to confirm the uniform thickness, stoichiometry, and lattice spacing of the MoS 2 layers. The MoS 2 crystals were deposited over the entire surface of the sample substrate. With a detailed discussion of the CVD setup and an explanation of the process parameters that influence nucleation and growth, this work opens a new platform for the repeatable synthesis of highly crystalline mono- or few-layer MoS 2 suitable for optoelectronic application.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

Domain wall enabled steep slope switching in MoS2 transistors towards hysteresis-free operation

Abstract The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS 2 transistors back-gated by single-layer polycrystalline PbZr 0.35 Ti 0.65 O 3 . The devices exhibit current switching ratios up to 8 × 10 6 within an ultra-low gate voltage window of $$V_{{{\mathrm{g}}}} = \pm \! 0.5$$ V g = ± 0.5 V and subthreshold swing (SS) as low as 9.7 mV decade −1 at room temperature, transcending the 60 mV decade −1 Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals the dominant role of the metastable polar states within domain walls in enabling the NC mode, which is corroborated by the relation between SS and domain wall density. Our findings shed light on a hysteresis-free mechanism for NC operation, providing a simple yet effective material strategy for developing low-power 2D nanoelectronics.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Probing the Electronic and Opto-Electronic Properties of Multilayer MoS 2 Field-Effect Transistors at Low Temperatures

Transition metal dichalcogenides (TMDs)-based field-effect transistors (FETs) are being investigated vigorously for their promising applications in optoelectronics. Despite the high optical response reported in the literature, most of them are studied at room temperature. To extend the application of these materials in a photodetector, particularly at a low temperature, detailed understanding of the photo response behavior of these materials at low temperatures is crucial. Here we present a systematic investigation of temperature-dependent electronic and optoelectronic properties of few-layers MoS 2 FETs, synthesized using the mechanical exfoliation of bulk MoS 2 crystal, on the Si/SiO 2 substrate. Our MoS 2 FET show a room-temperature field-effect mobility μ FE ~40 cm 2 ·V -1 ·s -1 , which increases with decreasing temperature, stabilizing at 80 cm 2 ·V -1 ·s -1 below 100 K. The temperature-dependent (50 K < T < 300 K) photoconductivity measurements were investigated using a continuous laser source λ = 658 nm (E = 1.88 eV) over a broad range of effective illuminating laser intensity, P eff (0.02 μW < P eff < 0.6 μW). Photoconductivity measurements indicate a fractional power dependence of the steady-state photocurrent. The room-temperature photoresponsivity (R) obtained in these samples was found to be ~2 AW -1 , and it increases as a function of decreasing temperature, reaching a maximum at T = 75 K. The optoelectronic properties of MoS 2 at a low temperature give an insight into photocurrent generation mechanisms, which will help in altering/improving the performance of TMD-based devices for various applications.

2D materials↗
DOE OSTI2024

Biaxial Tensile Strain Enhances Electron Mobility of Monolayer Transition Metal Dichalcogenides

Strain engineering can modulate the material properties of two-dimensional (2D) sem- iconductors for electronic and optoelectronic applications. Recent theory and experiments have found that uniaxial tensile strain can improve the electron mobility of monolayer MoS 2 , a 2D semiconductor, but the effects of biaxial strain on charge transport are not well-understood in 2D semiconductors. Here, we use biaxial tensile strain on flexible substrates to probe the electron mobility in monolayer WS 2 and MoS 2 transistors. Further, this approach experimentally achieves ~2× higher on-state current and mobility with ~0.3% applied biaxial strain in WS 2 , the highest mobility improvement at the lowest strain reported to date. We also examine the mechanisms behind this improvement through density functional theory simulations, concluding that the enhancement is primarily due to reduced intervalley electron-phonon scattering. These results underscore the role of strain engineering 2D semiconductors for flexible electronics, sensors, integrated circuits, and other opto-electronic applications.

2D materials↗
DOE OSTI2023

Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform

Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS 2 ) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS 2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS 2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm 2 V -1 s -1 . Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS 2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2024

Superionic fluoride gate dielectrics with low diffusion barrier for two-dimensional electronics

Exploration of new dielectrics with a large capacitive coupling is an essential topic in modern electronics when conventional dielectrics suffer from the leakage issue near the breakdown limit. Here, to address this looming challenge, we demonstrate that rare-earth metal fluorides with extremely low ion migration barriers can generally exhibit an excellent capacitive coupling over 20 μF cm -2 (with an equivalent oxide thickness of ~0.15 nm and a large effective dielectric constant near 30) and great compatibility with scalable device manufacturing processes. Such a static dielectric capability of superionic fluorides is exemplified by MoS 2 transistors exhibiting high on/off current ratios over 10 8 , ultralow subthreshold swing of 65 mV dec -1 and ultralow leakage current density of ~10 -6 A cm -2 . Therefore, the fluoride-gated logic inverters can achieve notably higher static voltage gain values (surpassing ~167) compared with a conventional dielectric. Furthermore, the application of fluoride gating enables the demonstration of NAND, NOR, AND and OR logic circuits with low static energy consumption. In particular, the superconductor–insulator transition at the clean-limit Bi 2 Sr 2 CaCu 2 O 8+δ can also be realized through fluoride gating. In conclusion, our findings highlight fluoride dielectrics as a pioneering platform for advanced electronic applications and for tailoring emergent electronic states in condensed matter.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS1985

Development of optimized detector/spectrophotometer technology for low background space astronomy missions

This program was directed towards a better understanding of some of the important factors in the performance of infrared detector arrays at low background conditions appropriate for space astronomy. The arrays were manufactured by Aerojet Electrosystems Corporation, Azusa. Two arrays, both bismuth doped silicon, were investigated: an AMCID 32x32 Engineering mosiac Si:Bi accumulation mode charge injection device detector array and a metal oxide semiconductor/field effect transistor (MOS-FET) switched array of 16x32 pixels.

Jones, B.↗
NASA NTRS1992

Remote hydrogen sensing techniques

The objective of this project is to evaluate remote hydrogen sensing methodologies utilizing metal oxide semi-conductor field effect transistors (MOS-FET) and mass spectrometric (MS) technologies and combinations thereof.

Perry, Cortes L.↗
NASA NTRS1973

Gyrator employing field effect transistors

A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 deg phase reversal is examined. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.

Hochmair, E. S.↗
DOE OSTI2020

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
NASA NTRS1993

Total Ionizing Dose Effects in 12-Bit Successive-Approximation Analog-To-Digital Converters

Analog-to-digital (A/D) converters are critical components in many space and military systems, and there have been numerous advances in A/D converter technology that have increased the resolution and conversion time. The increased performance is due to two factors: (1) advances in circuit design and complexity, which have increased the number of components and the integration density; and (2) new process technologies, such as BiCMOS, which provide better performance, cost, and smaller size in mixed-signal circuits. High-speed A/D converters, with conversion rates above 1 MHz, present a challenge to circuit designers and test engineers. Their complex architectures and high-performance specifications result in numerous possible failure modes when they are subjected to ionizing radiation. The dominant failure mode may depend on the specific application because the fundamental effects on MOS and bipolar transistors are strongly affected by bias conditions.

Lee, C. I.↗
DOE OSTI2024

Quantifying carrier density in monolayer MoS 2 by optical spectroscopy

The successful design and device integration of nanoscale heterointerfaces hinges upon precise manipulation of both ground- and excited-state charge carrier (electron and hole) densities. However, it is particularly challenging to quantify these charge carrier densities in nanoscale materials, leading to uncertainties in the mechanisms of many carrier density-dependent properties and processes. Here, we demonstrate a method that utilizes steady-state and transient absorption spectroscopies to correlate monolayer MoS 2 electron density with the easily measured metric of excitonic optical absorption quenching in a variety of mixed-dimensionality s-SWCNT/MoS 2 heterostructures. By employing a 2D phase-space filling model, the resulting correlation elucidates the relationship between charge density, local dielectric environment, and concomitant excitonic properties. The phase-space filling model is also able to describe existing trends from the literature on transistor-based measurements on MoS 2 , WS 2 , and MoSe 2 monolayers that were not previously compared to a physical model, providing additional support for our method and results. The findings provide a pathway to the community for estimating both ground- and excited-state carrier densities in a wide range of TMDC-based systems.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2026

Solid-state thermometry via ionic–electronic coupling in two-dimensional heterostructures

The coupling of ionic and electronic transport in solid-state systems offers new opportunities for realizing compact, energy-efficient sensing technologies, yet practical implementations remain limited. In this article, we introduce a two-dimensional iontronic platform based on field-effect transistors that integrate monolayer MoS 2 channels with van der Waals bimetallic thiophosphates ( AB P 2 X 6 , A = Li, Cu, Ag and so on; B = In, Sc and so on; and X = S and Se) as ionic gate dielectrics to realize on-chip thermometry. Specifically, we exploit thermally activated ion migration within the gate dielectric leading to conductance modulation in the MoS 2 channel for temperature sensing. We achieve ~1–2 °C resolution, fast electronic readout and subpicojoule energy consumption in an ultracompact footprint (~1 µm 2 ). Beyond thermometry, these results establish bimetallic thiophosphates as a versatile platform for solid-state iontronics and broaden the functional design space of van der Waals heterostructures for sensing, actuation and adaptive electronics.

42 ENGINEERING↗
NASA NTRS1966

Miniature electrometer preamplifier effectively compensates for input capacitance

Negative capacitance preamplifier using a dual MOS /Metal Oxide Silicon/ transistor in conjunction with bipolar transistors is used with intracellular microelectrodes in recording bioelectric potentials. Applications would include use as a pickup plate video amplifier in storage tube tests and for pH and ionization chamber measurements.

Burrous, C. N.↗
NASA NTRS1989

MCTs and IGBTs - A comparison of performance in power electronic circuits

There is a continuous demand for improvements in the quality of switching power devices, such as higher switching frequency, higher withstand voltage capability, larger current-handling capability, and lower conduction losses. However, for single-conduction-mechanism devices (SCRs, GTOs, BJTs, FETs), possessing all these features is probably unrealizable for physical reasons. An attractive solution appears to be double-mechanism devices, in which the features of both a minority carrier device (BJT or SCR) and a majority carrier device (MOSFET) are embedded. Both IGBTs (insulated-gate bipolar transistors) and MCTs (MOS-controlled thyristors) belong to this family of double-mechanism devices and promise to have a major impact on converter circuit signs. The authors deal with the major features of these two devices, pointing out those that are most critical to the design of converter topologies. In particular, the two devices have been tested both in a chopper and in two resonant link converter topologies, and the experimental results are reported.

Sul, S. K.↗
NASA NTRS1989

A parallel algorithm for switch-level timing simulation on a hypercube multiprocessor

The parallel approach to speeding up simulation is studied, specifically the simulation of digital LSI MOS circuitry on the Intel iPSC/2 hypercube. The simulation algorithm is based on RSIM, an event driven switch-level simulator that incorporates a linear transistor model for simulating digital MOS circuits. Parallel processing techniques based on the concepts of Virtual Time and rollback are utilized so that portions of the circuit may be simulated on separate processors, in parallel for as large an increase in speed as possible. A partitioning algorithm is also developed in order to subdivide the circuit for parallel processing.

Rao, Hariprasad Nannapaneni↗
DOE OSTI2024

Selected Area Manipulation of MoS 2 via Focused Electron Beam-Induced Etching for Nanoscale Device Editing

Here we demonstrate direct-write patterning of single and multilayer MoS 2 via a focused electron beam-induced etching (FEBIE) process mediated with the XeF 2 precursor. MoS 2 etching is performed at various currents, areal doses, on different substrates, and characterized using scanning electron and atomic force microscopies as well as Raman and photoluminescence spectroscopies. Scanning transmission electron microscopy reveals a sub-40 nm etching resolution and the progression of point defects and lateral etching of the consequent unsaturated bonds. The results confirm that the electron beam-induced etching process is minimally invasive to the underlying material in comparison to ion beam techniques, which damage the subsurface material. Single-layer MoS 2 field-effect transistors are fabricated, and device characteristics are compared for channels that are edited via the selected area etching process. The source–drain current at constant gate and source–drain voltage scale linearly with the edited channel width. Moreover, the mobility of the narrowest channel width decreases, suggesting that backscattered and secondary electrons collaterally affect the periphery of the removed area. Focused electron beam doses on single-layer transistors below the etching threshold were also explored as a means to modify/thin the channel layer. The FEBIE exposures showed demonstrative effects via the transistor transfer characteristics, photoluminescence spectroscopy, and Raman spectroscopy. While strategies to minimize backscattered and secondary electron interactions outside of the scanned regions require further investigation, here, we show that FEBIE is a viable approach for selective nanoscale editing of MoS 2 devices.

36 MATERIALS SCIENCE↗