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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

A Comparison of Ion Implantation at Room Temperature and Heated Ion Implantation on the Body Diode Degradation of Commercial 3.3 kV 4H-SiC Power MOSFETs

It has been demonstrated that basal plane dislocations (BPDs)-induced stacking faults (SFs) cause body diode degradation in commercial 4H-SiC power MOSFETs, especially with higher voltage ratings. BPDs originate from 4H-SiC boule, epi growth, and ion implantation. Considering the lower cost of ion implantation at room temperature (RT), this work investigates the potential of RT ion implantation replacing heated (HT) ion implantation by comparing the influence of both ion implantations on the body diode degradation of commercial 3.3 kV 4H-SiC power MOSFETs. We demonstrate with long-term (up to 1000 hours) forward current stress that RT implantation can keep the body diode degradation of 3.3 kV 4H-SiC power MOSFETs within the specification limits compared with HT implantation.

4H-SiC↗
DOE OSTI2015

SU-E-T-196: Comparative Analysis of Surface Dose Measurements Using MOSFET Detector and Dose Predicted by Eclipse - AAA with Varying Dose Calculation Grid Size

Purpose: Skin dose can be the limiting factor and fairly common reason to interrupt the treatment, especially for treating head-and-neck with Intensity-modulated-radiation-therapy(IMRT) or Volumetrically-modulated - arc-therapy (VMAT) and breast with tangentially-directed-beams. Aim of this study was to investigate accuracy of near-surface dose predicted by Eclipse treatment-planning-system (TPS) using Anisotropic-Analytic Algorithm (AAA)with varying calculation grid-size and comparing with metal-oxide-semiconductor-field-effect-transistors(MOSFETs)measurements for a range of clinical-conditions (open-field,dynamic-wedge, physical-wedge, IMRT,VMAT). Methods: QUASAR™-Body-Phantom was used in this study with oval curved-surfaces to mimic breast, chest wall and head-and-neck sites.A CT-scan was obtained with five radio-opaque markers(ROM) placed on the surface of phantom to mimic the range of incident angles for measurements and dose prediction using 2mm slice thickness.At each ROM, small structure(1mmx2mm) were contoured to obtain mean-doses from TPS.Calculations were performed for open-field,dynamic-wedge,physical-wedge,IMRT and VMAT using Varian-21EX,6&15MV photons using twogrid-sizes:2.5mm and 1mm.Calibration checks were performed to ensure that MOSFETs response were within ±5%.Surface-doses were measured at five locations and compared with TPS calculations. Results: For 6MV: 2.5mm grid-size,mean calculated doses(MCD)were higher by 10%(±7.6),10%(±7.6),20%(±8.5),40%(±7.5),30%(±6.9) and for 1mm grid-size MCD were higher by 0%(±5.7),0%(±4.2),0%(±5.5),1.2%(±5.0),1.1% (±7.8) for open-field,dynamic-wedge,physical-wedge,IMRT,VMAT respectively.For 15MV: 2.5mm grid-size,MCD were higher by 30%(±14.6),30%(±14.6),30%(±14.0),40%(±11.0),30%(±3.5)and for 1mm grid-size MCD were higher by 10% (±10.6), 10%(±9.8),10%(±8.0),30%(±7.8),10%(±3.8) for open-field, dynamic-wedge, physical-wedge, IMRT, VMAT respectively.For 6MV, 86% and 56% of all measured values agreed better than ±20% for 1mm and 2.5mm grid-sizes respectively. For 18MV, 56% and 18% of all measured-values agreed better than ±20% for 1mm and 2.5mm grid-sizes respectively. Conclusion: Reliable Skin-dose calculations by TPS can be very difficult due to steep dose-gradient and inaccurate beam-modelling in buildup region.Our results showed that Eclipse over-estimates surface-dose.Impact of grid-size is also significant,surface-dose increased up to 40% from 1mm to 2.5mm,however, 1mm calculated-values closely agrees with measurements. Due to large uncertnities in skin-dose predictions from TPS, outmost caution must be exercised when skin dose is evaluated,a sufficiently smaller grid-size(1mm)can improve the accuracy and MOSFETs can be used for verification.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2025

Investigation of the Effect of Gate Oxide Screening with Adjustment Pulse on Commercial SiC Power MOSFETs

This paper presents a method to recover the negative threshold voltage shift during high field gate oxide screening of 1.2 kV 4H-SiC MOSFETs with an additional adjustment gate voltage pulse. To reduce field failure rates of the MOSFETs in operation, manufacturers perform a screening treatment to remove devices with extrinsic defects in the oxide. Current gate oxide screening procedures are limited to oxide fields at or below ~9 MV/cm for short durations (<1 s), which is not enough to remove all the devices with extrinsic defects. The results show that by implementing a lower field gate pulse, the threshold voltage shift can be partially recovered, and therefore the maximum screening field and time can be increased. However, both the initial screening pulse and the adjustment pulse require careful calibration to prevent significant degradation of the device threshold voltage, on-resistance, interface state density, or intrinsic lifetime. With a well calibrated set of pulses, higher screening fields can be utilized without significantly damaging the devices. This leads to an improvement in the overall screening efficiency of the process, reducing the number of devices with extrinsic oxide defects entering the field, and improving the reliability of the SiC MOSFETs in operation.

42 ENGINEERING↗
NASA NTRS2011

Prognostics of Power Mosfets Under Thermal Stress Accelerated Aging Using Data-Driven and Model-Based Methodologies

An approach for predicting remaining useful life of power MOSFETs (metal oxide field effect transistor) devices has been developed. Power MOSFETs are semiconductor switching devices that are instrumental in electronics equipment such as those used in operation and control of modern aircraft and spacecraft. The MOSFETs examined here were aged under thermal overstress in a controlled experiment and continuous performance degradation data were collected from the accelerated aging experiment. Dieattach degradation was determined to be the primary failure mode. The collected run-to-failure data were analyzed and it was revealed that ON-state resistance increased as die-attach degraded under high thermal stresses. Results from finite element simulation analysis support the observations from the experimental data. Data-driven and model based prognostics algorithms were investigated where ON-state resistance was used as the primary precursor of failure feature. A Gaussian process regression algorithm was explored as an example for a data-driven technique and an extended Kalman filter and a particle filter were used as examples for model-based techniques. Both methods were able to provide valid results. Prognostic performance metrics were employed to evaluate and compare the algorithms.

Electrolytic capacitors↗
NASA NTRS2012

Prognostics Approach for Power MOSFET Under Thermal-Stress

The prognostic technique for a power MOSFET presented in this paper is based on accelerated aging of MOSFET IRF520Npbf in a TO-220 package. The methodology utilizes thermal and power cycling to accelerate the life of the devices. The major failure mechanism for the stress conditions is dieattachment degradation, typical for discrete devices with leadfree solder die attachment. It has been determined that dieattach degradation results in an increase in ON-state resistance due to its dependence on junction temperature. Increasing resistance, thus, can be used as a precursor of failure for the die-attach failure mechanism under thermal stress. A feature based on normalized ON-resistance is computed from in-situ measurements of the electro-thermal response. An Extended Kalman filter is used as a model-based prognostics techniques based on the Bayesian tracking framework. The proposed prognostics technique reports on preliminary work that serves as a case study on the prediction of remaining life of power MOSFETs and builds upon the work presented in [1]. The algorithm considered in this study had been used as prognostics algorithm in different applications and is regarded as suitable candidate for component level prognostics. This work attempts to further the validation of such algorithm by presenting it with real degradation data including measurements from real sensors, which include all the complications (noise, bias, etc.) that are regularly not captured on simulated degradation data. The algorithm is developed and tested on the accelerated aging test timescale. In real world operation, the timescale of the degradation process and therefore the RUL predictions will be considerable larger. It is hypothesized that even though the timescale will be larger, it remains constant through the degradation process and the algorithm and model would still apply under the slower degradation process. By using accelerated aging data with actual device measurements and real sensors (no simulated behavior), we are attempting to assess how such algorithm behaves under realistic conditions.

Power MOSFET PHM↗
NASA NTRS2016

Single-Event Latchup Testing of the Micrel MIC4424 Dual Power MOSFET Driver

We conducted 47 exposures of four different MIC4424 devices and did not observe any SEL or high-current events. This included worst-case conditions with a LET of 81 MeV-sq cm/mg, applied voltage of 18.5 V, a case temperature greater than 120 C, and a final fluence of 1x10(exp 7)/sq cm. We also monitored both the outputs for the presence of SETs. While the period of the 1 MHz square wave was slightly altered in some cases, no pulses were added or deleted. 1. Purpose: The purpose of this testing is to characterize the BiCMOS/DMOS Micrel MIC4424 dual, non-inverting MOSFET driver for single-event latchup (SEL) susceptibility. These data will be used for flight lot evaluation purposes. 2. Devices Tested: The MIC4423/4424/4425 family are highly reliable BiCMOS/DMOS buffer/driver MOSFET drivers. They are higher output current versions of the MIC4426/4427/4428. They can survive up to 5V of noise spiking, of either polarity, on the ground pin. They can accept, without either damage or logic upset, up to half an amp of reverse current (either polarity) forced back into their outputs. Primarily intended for driving power MOSFETs, the MIC4423/4424/4425 drivers are suitable for driving other loads (capacitive, resistive, or inductive) which require low-impedance, high peak currents, and fast switching times. Heavily loaded clock lines, coaxial cables, or piezoelectric transducers are some examples. The only known limitation on loading is that total power dissipated in the driver must be kept within the maximum power dissipation limits of the package. Five (5) parts were provided for SEL testing. We prepared four parts for irradiation and reserved one piece as an un-irradiated control. More information about the devices can be found in Table 1. The parts were prepared for testing by removing the lid from the CDIP package to expose the target die. The parts were then soldered to small copper circuit adapter boards for easy handling. These parts are fabricated in a bulk BiCMOS/DMOS technology. Since we do not know the number of overlayers used in the fabrication processes, linear energy transfer calculations are determined based on the top-surface incident ion species and kinetic energy.

Power MOSFET↗
DOE OSTI2017

88 kilowatt automotive inverter with new 900 Volt silicon carbide MOSFET technology

This final report is on the design and experimental verification of a 200 kVA traction inverter using three 900 V, 2.5 mΩ, SiC MOSFET-based half-bridge power modules comprising the power stage. Each dual power module contains four 900 V, 10 mΩ SiC MOSFETs per switch position and uses synchronous conduction to achieve high average and peak efficiencies over its entire operating region to meet the demands of hybrid, plug-in hybrid, and extended-range electrified vehicle architectures. Significant performance improvement, via conduction, switching, and reverse-recovery loss metrics, from this SiC MOSFET-based inverter—especially at light load conditions—will be discussed.

30 DIRECT ENERGY CONVERSION↗
DOE OSTI2019

Demonstration and analysis of a 600 V, 10 A, 4H-SiC lateral single RESURF MOSFET for power ICs applications

This paper reports the demonstration of a 600 V 4H-SiC lateral MOSFET with a large current handling capability (10 A). To achieve a high breakdown voltage in a lateral architecture, a REduced SURface Field (RESURF) structure was implemented to alleviate surface electric field crowding. A single RESURF (P-top) design on an N-drift on a 6-in. N+ substrate demonstrated a voltage supporting capability of 120 V/ μ m, resulting in a breakdown voltage of 600 V. The total width of 198 mm for the interdigitated gate fingers was designed to accomplish the high current capability. It turned out that, for relatively low voltage SiC lateral MOSFETs (<600 V), more focus needs to be placed on achieving a low channel, contact, metal, and JFET region resistance than a low drift layer resistance to further improve the on-resistance. Device design, fabrication, and electrical characterization of the proposed 600 V, 10 A, 4H-SiC lateral single RESURF MOSFETs are discussed in this paper.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2018

Characterization and Comparison of Trench and Planar Silicon Carbide (SiC) MOSFET at Different Temperatures

In this paper, the static and dynamic characteristics of discrete 650 V and 1200 V trench TO 247 SiC MOSFET is evaluated and compared with a similar current rating 1200 V planar gate discrete TO 247 SiC MOSFET. The new trench MOSFET has promising application for vehicle charging and auxiliary power supply application due to the lower on-state resistance and lower capacitance. Static characteristics for these devices are evaluated using a curve tracer for different device junction temperature A common double pulse test (DPT) platform is developed to evaluate the switching loss at different device junction temperature ranging from 25°C to 175°C. The experimental setup and results are presented for different load currents and temperature.

Anwar, Saeed↗
DOE OSTI2013

Engineering Nanowire n-MOSFETs at $L_{g}<8~{\rm nm}$

As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths ( Lg ) are scaled to lengths shorter than Lg <; 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg <; 8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs.

Engineering↗
NASA NTRS1990

Calculating Second-Order Effects in MOSFET's

Collection of mathematical models includes second-order effects in n-channel, enhancement-mode, metal-oxide-semiconductor field-effect transistors (MOSFET's). When dimensions of circuit elements relatively large, effects neglected safely. However, as very-large-scale integration of microelectronic circuits leads to MOSFET's shorter or narrower than 2 micrometer, effects become significant in design and operation. Such computer programs as widely-used "Simulation Program With Integrated Circuit Emphasis, Version 2" (SPICE 2) include many of these effects. In second-order models of n-channel, enhancement-mode MOSFET, first-order gate-depletion region diminished by triangular-cross-section deletions on end and augmented by circular-wedge-cross-section bulges on sides.

Benumof, Reuben↗
NASA NTRS1999

Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub 50 nm MOSFETs: a Statistical 3D 'Atomistic' Simulation Study

A 3D 'atomistic' simulation study of random dopant induced threshold voltage fluctuations and lowering in sub 50 nm MOSFETs is presented. The attention is focused mainly on devices with 30 nm effective channel length which represent the expected level of scaling at the end of the Silicon Roadmap. An efficient algorithm, based on a single 3D ap solution of the Poisson equation and a simplified current continuity equation, is used in the simulations. Large samples of microscopically different devices (typically 200) arc used in order to obtain statistically reliable results. The influence of different aspects of the conventional MOSFET design on the threshold voltage fluctuations and lowering are investigated. Results for fluctuation resistant device architectures based on low-doped epitaxial channel MOSFETs are also presented.

Asenov, Asen↗
NASA NTRS2000

Statistical 3D 'Atomistic' Simulation of Decanano MOSFETs

A 3D statistical 'atomistic' simulation technique has been developed to study the effect of the random dopant induced parameter fluctuations in aggressively scaled MOSFETs. Efficient implementation of the 'atomistic' simulation approach has been used to investigate the threshold voltage standard deviation and lowering in the case of uniformly doped MOSFETs, and in fluctuation-resistant architectures utilising epitaxial-layers and delta-doping. The effect of the random doping in the polysilicon gate on the threshold voltage fluctuations has also been thoroughly investigated. The influence of a single-charge trapping on the channel conductivity in decanano MOSFETs is studied in the 'atomistic' framework as well. Quantum effects are taken into consideration in our 'atomistic' simulations using the density gradient formalism.

Asenov, Asen↗
NASA NTRS2001

2-D Modeling of Nanoscale MOSFETs: Non-Equilibrium Green's Function Approach

We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Electron-electron interaction is treated within Hartree approximation by solving NEGF and Poisson equations self-consistently. For the calculations presented here, parallelization is performed by distributing the solution of NEGF equations to various processors, energy wise. We present simulation of the "benchmark" MIT 25nm and 90nm MOSFETs and compare our results to those from the drift-diffusion simulator and the quantum-corrected results available. In the 25nm MOSFET, the channel length is less than ten times the electron wavelength, and the electron scattering time is comparable to its transit time. Our main results are: (1) Simulated drain subthreshold current characteristics are shown, where the potential profiles are calculated self-consistently by the corresponding simulation methods. The current predicted by our quantum simulation has smaller subthreshold slope of the Vg dependence which results in higher threshold voltage. (2) When gate oxide thickness is less than 2 nm, gate oxide leakage is a primary factor which determines off-current of a MOSFET (3) Using our 2-D NEGF simulator, we found several ways to drastically decrease oxide leakage current without compromising drive current. (4) Quantum mechanically calculated electron density is much smaller than the background doping density in the poly silicon gate region near oxide interface. This creates an additional effective gate voltage. Different ways to. include this effect approximately will be discussed.

Svizhenko, Alexei↗
NASA NTRS2009

Effects of Lightning Injection on Power-MOSFETs

Lightning induced damage is one of the major concerns in aircraft health monitoring. Such short-duration high voltages can cause significant damage to electronic devices. This paper presents a study on the effects of lightning injection on power metal-oxide semiconductor field effect transistors (MOSFETs). This approach consisted of pin-injecting lightning waveforms into the gate, drain and/or source of MOSFET devices while they were in the OFF-state. Analysis of the characteristic curves of the devices showed that for certain injection modes the devices can accumulate considerable damage rendering them inoperable. Early results demonstrate that a power MOSFET, even in its off-state, can incur considerable damage due to lightning pin injection, leading to significant deviation in its behavior and performance, and to possibly early device failures.

Celaya, Jose↗
NASA NTRS2016

Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.

Ikpe, Stanley A.↗
NASA NTRS2017

Recent Radiation Test Results for Trench Power MOSFETs

Single-event effect (SEE) radiation test results are presented for various trench-gate power MOSFETs. The heavy-ion response of the first (and only) radiation-hardened trench-gate power MOSFET is evaluated: the manufacturer SEE response curve is verified and importantly, no localized dosing effects are measured, distinguishing it from other, non-hardened trench-gate power MOSFETs. Evaluations are made of n-type commercial and both n- and p-type automotive grade trench-gate device using ions comparable to of those on the low linear energy transfer (LET) side of the iron knee of the galactic cosmic ray spectrum, to explore suitability of these parts for missions with higher risk tolerance and shorter duration, such as CubeSats. Part-to-part variability of SEE threshold suggests testing with larger sample sizes and applying more aggressive derating to avoid on-orbit failures. The n-type devices yielded expected localized dosing effects including when irradiated in an unbiased (0-V) configuration, adding to the challenge of inserting these parts into space flight missions.

Schottky Diodes↗
NASA NTRS2019

Mechanisms of Heavy Ion-Induced Single Event Burnout in 4H-SiC Power MOSFETs

This describes the mechanisms behind the failure of 4H-SiC Power MOSFETs when struck by a heavy ion. The modeled device is designed to simulate a commercially available 1200 V power MOSFET and the ion simulated is a silver ion with a Linear Energy Transfer of 46 MeV-cm2/mg commonly used in single event effect (SEE) testing. The device is shown in simulation to fail near 500 V, which is in close agreement to experiments. These simulations go to show that the failure of SiC MOSFET occurs near the interface between the epi and substrate layers due to the rapid increase of the electric field in that region and destruction of the device from impact ionization. From this, two designs were proposed and investigated that would help to mitigate the electric field in these regions and improve the device's tolerance to single-event burnout (SEB). The new designs increased the voltage at which SEB occurs from 500 V to over 900 V and increased the Ron,sp by only 5%.

Mcpherson, Joseph A.↗