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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4

TCAD-Machine Learning Enabled TID Compact Model Development for Commercial SiC MOSFET

We propose a TCAD (Technology Computer Aided Design)-machine learning coupled approach that combines a TCAD tool (Charon), optimization/uncertainty quantification tool (Dakota), surrogate models, and Bayesian learning capabilities. The coupling approach is used for accurate modeling and calibration of total ionizing dose (TID) induced threshold voltage (V th ) shifts in Commercial-Off-The-Shelf (COTS) semiconductor devices and to develop physics-informed TID compact models. This versatile approach is applied to model the TID effect in an exemplar COTS 3.3 kV SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). With the Charon-Dakota coupling, we can determine key device geometry and doping values based on device physics, which are difficult to obtain or not available for COTS devices but important for TCAD simulation; additionally, we can efficiently generate thousands of simulation results in a large parameter space, which makes it possible to develop data-driven surrogate models and perform Bayesian calibration. Utilizing the full tool-coupling approach, we achieve calibrated TCAD simulation models that accurately capture the average TID-induced V th shifts behavior with total doses and V th shifts saturation at high doses as observed in experimental data. More importantly, the calibrated TCAD simulations are obtained with determined TID model parameters (e.g., hole trap density and capture cross section) values that contain well quantified uncertainties. Furthermore, we can isolate and quantify the noises that are not captured by the TCAD models but exist in the measured data due to measurements and devices variabilities. Lastly, the calibrated surrogate models are used to develop physics-informed TID compact models. The method is generalizable to other devices and/or radiation conditions with few modifications and can provide well-determined uncertainties.

COTS↗

Investigations into the Power MOSFET SEGR Phenomenon and its Physical Mechanism

The state of understanding of the destructive SEGR event in power MOSFETs is relatively mature with large published efforts, both experimental and theoretical. However, gasps remain in the uderstanding of the phenomenon, including unexplained anomalies, emperical-only dependencies on some important device and incident ion physical parameters, and limited insight into latent effets.

MOSFET SEGR↗

Current Leakage Evolution in Partially Gate Raptured Power MOSFETs

It has been observed that power MOSFETs can experience an SEGR and continue to function with altered parameters. We propose that there are three different types of SEGR modes; the micro-break, the thermal runaway, and the avalanche breakdown. Data that demonstrates these stages of device failure are presented as well as a proposed model for the micro-break. Brief discussions of the other modes, based on analysis combined with our interpretations of the older literature, are also given.

metal oxide semiconductor field-effect transistors↗

Radiation Hardness Study on SiC Power MOSFETs

As an emerging technology, silicon carbide (SiC) power MOSFETs are showing great potential for higher temperature/power rating, higher efficiency, and reduction in size and weight, which makes this technology ideal for high temperature, harsh environment applications such as downhole, medical, avionic, or even space applications. Radiation tolerance therefore becomes a critical aspect of the device performance in such environments. In this work, we explored radiation hardness of SiC devices to total ionizing dose (TID), neutron-induced single-event burnout (SEB), and heavy-ion induced single-event effects (SEE).

SiC↗

Design and Testing of a Hard-Fault Protection Circuit for a 1 kV SiC MOSFET Inverter

Due to increasingly high DC link voltages and further advancements in the current density of silicon carbide (SiC) MOSFETs, it has become evident that conventional IGBT protection methods are not sufficient to prevent exceeding the current rating of these devices during low-inductance fault events. This paper explores the use of an air core Rogowski coil topology to mitigate these hard fault events. The design of this circuit resulted in safe shutdown of a low impedance phase-to-phase fault in under one microsecond, tested up to DC link voltages of 1 kV. This paper details the theory, design, simulation, and successful test results of this method.

hard fault protection↗

NASA Engineering and Safety Center Technical Bulletin No. 10-01: Power MOSFET Thermal Instability

In the quest for faster switching times and lower “on resistance” the Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET), produced since 1998, has achieved most intended goals. Unfortunately, lower “on resistance” and higher switching speeds in the designs now being produced allow the charge carrier dominated region to develop conditions that could lead to thermal runaway. Temperatures above 450º C on any location within the part can cause the metals to begin migrating causing a fatal short circuit.

Metal-Oxide Semiconductor Field-Effect Transistor ↗

Single Event Effects Test Report IXYS IXTA96P085T P-Channel -85V MOSFET

This study was undertaken to determine the destructive single event effect and degradation susceptibility of the IXTA96P085T P-Channel -85V MOSFET from IXYS. The device was monitored for destructive single event effects and degradation during exposure to a heavy ion beam at the Berkeley Accelerator Space Effects (BASE) Facility at the Lawrence Berkeley National Laboratory (LBNL). Gate and drain currents were measured during irradiation and a basic set of electrical characterizations was performed following each fluence exposure to assess heavy ion induced damage. The test date was April 10, 2024. This characterization is application specific.

MOSFET↗

Single Event Effects Test Report Vishay Siliconix Si7113DN P-Channel 100V MOSFET

This study was undertaken to determine the destructive single event effect and degradation susceptibility of the Si7113DN P-Channel 100V MOSFET from Vishay Siliconix. The device was monitored for destructive single event effects and degradation during exposure to a heavy ion beam at the Berkely Accelerator Space Effects (BASE) Facility at the Lawrence Berkely National Laboratory (LBNL).

MOSFET↗

Design and Development of a Fluid Immersion Cooled, SiC MOSFET, 37.5 kW, Bi-Directional Motor Converter

NASA's SUb-sonic Single Aft eNgine (SUSAN) aircraft is a concept aircraft whose architecture is that of a subsonic regional jet transport aircraft. SUSAN contains a single turbofan engine coupled to an electrified aircraft propulsion (EAP) system. To provide a path towards this goal, a 25% scale version of the SUSAN aircraft is being researched. A main component of the 25% power train is the Motor And Generator Intelligent Converter (MAGIC). This paper presents the design, development, and initial test results from MAGIC, a 37.5 kW, fluid immersion cooled, silicon carbide (SiC) MOSFET-based, bi-directional converter and controller.

PAO↗

Design and Development of a Fluid Immersion Cooled, SiC MOSFET, 37.5 kW, Bi-Directional Motor Converter

NASA's SUb-sonic Single Aft eNgine (SUSAN) aircraft is a concept aircraft whose architecture is that of a subsonic regional jet transport aircraft. SUSAN contains a single turbofan engine coupled to an electrified aircraft propulsion (EAP) system. To provide a path towards this goal, a 25% scale version of the SUSAN aircraft is being researched. A main component of the 25% power train is the Motor And Generator Intelligent Converter (MAGIC). This paper presents the design, development, and initial test results from MAGIC, a 37.5 kW, fluid immersion cooled, silicon carbide (SiC) MOSFET-based, bi-directional converter and controller.

Immersion↗

MOSFET analog memory circuit achieves long duration signal storage

Memory circuit maintains the signal voltage at the output of an analog signal amplifier when the input signal is interrupted or removed. The circuit uses MOSFET /Metal Oxide Semiconductor Field Effect Transistor/ devices as voltage-controlled switches, triggered by an external voltage-sensing device.

Source record↗