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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Quantifying Dynamic On-State Resistance of GaN HEMTs for Power Converter Design via a Survey of Low and High Voltage Devices

Designing and optimizing high switching frequency, ultra-efficient converters requires detailed knowledge of the behavior and parasitic parameters for both active and passive components. Recently, wide bandgap transistors have enabled simultaneous increases in both switching frequency and efficiency due to higher maximum operating junction temperature limits, lower dc on-state resistances, and reduced parasitic inductances and capacitances. Yet, the early acceptance of gallium-nitride (GaN) switches was plagued by detrimental dynamic on-state resistance effects. This complex phenomenon for GaN devices is characterized by deviations in on-state resistance from dc operating characteristics based on design choices such as the magnitude and duration of both voltage and current stress, switching mode, and junction temperature. While device manufacturers have made improvements compared to early generation devices, experimental evidence from a survey of commercial GaN transistors highlight measurable change in on-state resistance still exists due to variations in voltage stress during hard-switching operation. After sharing insights for obtaining low noise measurements, an analysis method along with two metrics are proposed to characterize dynamic on-state resistance measurements for power electronics designers. Furthermore, quantifying the performance of GaN devices with standardized metrics facilitates a fair comparison between different GaN device technologies during converter development, enables manufacturing qualification for GaN switches, and provides a benchmark to catalyze improvement for the next generation of GaN device development.

14 SOLAR ENERGY↗
NASA NTRS1975

Low-noise room-temperature and cryogenic mixers for 80-120 GHz

A description is given of two new mixers designed to operate in the 80-120-GHz range on 36-ft radio telescope. It is shown that for a hard-driven diode the parasitic resistance and capacitance are the primary factors influencing the design of the diode mount. A room-temperature mixer is described which achieves a single-sideband (SSB) conversion loss (L) of 5.5 dB, and a SSB noise temperature (Tm) of 500 K (excluding the IF contribution) with a 1.4-GHz IF. A cryogenically cooled version, using a quartz structure to support the diode chip and contact whisker, achieves values of L = 5.8 dB and Tm = 300 K with a 4.75-GHz IF. The mixers use high-quality Schottky-barrier diodes in a one-quarter-height waveguide mount.

Kerr, A. R.↗
NASA NTRS1992

Analysis of shielded CPW discontinuities with air-bridges

The effect of air-bridges on the performance of various coplanar waveguides (CPW) discontinuities is studied. Specifically, the coupled open-end CPW's and the short-end shunt CPW stub discontinuities are considered. The high frequency effect of the air-bridge is evaluated using a hybrid technique. At first, the frequency dependent equivalent circuit of the planar discontinuity without the air-bridge is derived using the Space Domain Integral Equation (SDIE) method. Then, the circuit is modified by incorporating the air-bridge's parasitic inductance and capacitance which are evaluated using a simple quasi-static model. The frequency response of each discontinuity with and without the air-bridge is studied and the scattering parameters are plotted in the frequency range 30-50 GHz for typical CPW dimensions.

Dib, N. I.↗
NASA NTRS1992

Negative Differential Resistance (NDR) frequency conversion with gain

The dependence of the I-V characteristic of the negative differential resistance (NDR) devices on the power level and frequency of the rf input signal has been theoretically analyzed with a modified large- and small-signal nonlinear circuit analysis program. The NDR devices we used in this work include both the tunnel diode (without the antisymmetry in the I-V characteristic) and resonant-tunneling devices (with the antisymmetry in the I-V characteristic). Absolute negative conductance can be found from a zero-biased resonant tunneling device when the applied pump power is within a small range. This study verifies the work of Sollner et al. Variable negative conductances at the fundamental and harmonic frequencies can also be obtained from both the unbiased and biased tunnel diodes. The magnitude of the negative conductances can be adjusted by varying the pump amplitude -- a very useful circuit property. However, the voltage range over which the negative conductance occurs moves towards the more positive side of the voltage axis with increasing frequency. Furthermore, the range of the pumping amplitude to obtain negative conductance varies with the parasitics (resistance and capacitance) of the device. The theoretical observation of the dependence of the I-V characteristic of the NDR devices on the power and frequency of the applied pump signal is supported by the experimental results. In addition, novel functions of a NDR device such as self-oscillating frequency multiplier and mixer with gain have been experimentally demonstrated. The unbiased oscillator have also been successfully realized with a NDR device with an antisymmetrical I-V characteristic. Finally, the applications of these device functions will be discussed.

Hwu, R. J.↗
DOE OSTI2025

Correcting impedance measurements for background parasitics to characterize circuit components in cryogenic environments

Predictable circuit response is a critical prerequisite for accurate electronic measurements. Here, we describe a powerful yet straightforward experimental method and analysis model that utilizes an affordable LCR meter in conjunction with an in situ parasitic-impedance background-correction procedure to measure the temperature-dependent impedance (magnitude and phase) of up to ten individual passive circuit elements in a single cryostat run. We show how the model unambiguously identified a ∼20× drop in capacitance for 22 μF 5XR multilayer ceramic capacitors cooled from 300 K to 360 mK in an environment with a parasitic capacitance of ∼300 pF. The same experimental procedure, based on a simple two-wire measurement, was also used to measure 10 and 22 pF thin-film capacitors and 100 MΩ thick-film resistors. The results showed that the resistor values increased by up to an order of magnitude when the devices were cooled from 300 K to 360 mK. Most importantly, we showed that the simple data-acquisition method, coupled with our analysis model, enabled the measurement of component parasitics, and effectively extended the accuracy of a commercial LCR meter beyond its manufacturer-guaranteed values for a wide range of measurement frequencies. We also showed that, in the current configuration, our simple approach is limited to a capacitance accuracy of ∼10 pF.

Carpenter, R. J. [Santa Clara Univ., Santa Clara, ↗
DOE OSTI2025

Development of a capacitance measurement for pulsed magnetic fields

Capacitance measurements are crucial for probing the electrical properties of materials. In this study, we develop and implement a capacitance measurement technique optimized for pulsed magnetic fields. Our approach employs an auto-balancing bridge method, leveraging a high-bandwidth transimpedance amplifier to mitigate parasitic contributions from coaxial cables. This technique enables precise capacitance measurements in rapidly changing magnetic fields, as demonstrated in experiments on the magnetoelectric material NiCo 2 TeO 6 . The results reveal strong magnetoelectric coupling, including a pronounced hysteresis in capacitance that coincides with magnetization measurements and an enhanced energy dissipation peak at high sweep rates. Compared to traditional LCR meter measurements in DC fields, our method exhibits excellent agreement while providing additional insight into field-induced phase transitions. This work establishes a robust methodology for capacitance measurements under extreme conditions and opens new opportunities for studying multiferroic and correlated electron systems under high magnetic fields.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2021

Liquid-Cooled Heat Sink Optimization for Thermal Imbalance Mitigation in Wide-Bandgap Power Modules

Power semiconductor die placement on substrates used in high-power modules is generally optimized to minimize electrical parasitic (e.g., stray inductance, common-mode capacitance), taking into account the minimum spacing between semiconductor dies for thermal decoupling. The layout assumes sufficient heat spreading and transfer from dies to the cooling structure. Insulated metal substrate-based power module designs may lead to asymmetrical thermal resistance across the dies, which may cause significant temperature differences among the devices. Such unintentional thermal asymmetries can lead to oversizing the cooling system design or underusing the semiconductor power processing capability. This article proposes a thermal imbalance mitigation method that uses evolutionary optimized liquid-cooled heat sinks to improve the thermal loading among devices.

42 ENGINEERING↗
NASA NTRS1978

Semi hemi antenna

The University of Michigan minipod, which is released from a balloon and floats down on a parachute, is designed for stratospheric testing. The present paper briefly describes the evolution of antenna designs for the minipod 1.5 GHz transceiver, which communicates with and relays information to an aircraft and ground station. The following stages are noted: ordinary monopole, crossed dipole, capacitative antenna, fat monopole, the addition of parasitic elements, and a thinner monopole with taper.

Repucci, T. A.↗
NASA NTRS2003

RF Frequency Oscillations in the Early Stages of Vacuum Arc Collapse

RF frequency oscillations may be produced in a typical capacitive charging / discharging pulsed power system. These oscillations may be benign, parasitic, destructive or crucial to energy deposition. In some applications, proper damping of oscillations may be critical to proper plasma formation. Because the energy deposited into the plasma is a function of plasma and circuit conditions, the entire plasma / circuit system needs to be considered as a unit To accomplish this, the initiation of plasma is modeled as a time-varying, non-linear element in a circuit analysis model. The predicted spectra are compared to empirical power density spectra including those obtained from vacuum arcs.

Griffin, Steven T.↗
NASA NTRS1990

High power density dc-to-dc converters for aerospace applications

Three dc-to-dc converter topologies aimed at high-power high-frequency applications are introduced. Major system parasitics, namely, the leakage inductance of the transformer and the device output capacitance are efficiently utilized. Of the three circuits, the single-phase and three-phase versions of the dual active bridge topology demonstrate minimal stresses, better utilization of the transformer, bidirectional, and buck-boost modes of operation. All circuits operate at a constant switching frequency, thus simplifying design of the reactive elements. The power transfer characteristics and soft-switching regions on the Vout-Iout plane are identified. Two coaxial transformers with different cross-sections were built for a rating of 50 kVA. Based on the single-phase dual active bridge topology, a 50 kW, 50 kHz converter operating at an input voltage of 200 Vdc and an output voltage of 1600 Vdc was fabricated. Characteristics of current-fed output make the dual active bridge topologies amenable to paralleling and hence extension to megawatt power levels. Projections to a 1 MW system operating from a 500 Vdc input, at an output voltage of 10 kVdc and a switching frequency of 50 kHz, using MOS-controlled thyristors, coaxially wound transformers operating at three times the present current density with cooling, and multilayer ceramic capacitors, suggests an overall power density of 0.075 to 0.08 kg/kW and an overall efficiency of 96 percent.

Divan, Deepakraj M.↗
DOE OSTI2023

Enhancing the electron mobility in Si-doped (010) β-Ga 2 O 3 films with low-temperature buffer layers

We demonstrate a new substrate cleaning and buffer growth scheme in β-Ga 2 O 3 epitaxial thin films using metal–organic vapor phase epitaxy (MOVPE). For the channel structure, a low-temperature (LT, 600 °C) un-doped Ga 2 O 3 buffer was grown, followed by a transition layer to a high-temperature (HT, 810 °C) Si-doped Ga 2 O 3 channel layers without growth interruption. The (010) Ga 2 O 3 Fe-doped substrate cleaning uses solvent cleaning, followed by additional hydrofluoric acid (49% in water) treatment for 30 min before the epilayer growth. This step is shown to compensate the parasitic Si channel at the epilayer–substrate interface that originates from the substrate polishing process or contamination from the ambient. From secondary ion mass spectroscopy (SIMS) analysis, the Si peak atomic density at the substrate interface is found to be several times lower than the Fe atomic density in the substrate—indicating full compensation. The elimination of the parasitic electron channel at the epi–substrate interface was also verified by electrical (capacitance–voltage profiling) measurements. In the LT-grown (600 °C) buffer layers, it is seen that the Fe forward decay tail from the substrate is very sharp, with a decay rate of ∼9 nm/dec. X-ray off-axis rocking curve ω-scans show very narrow full width at half maximum (FWHM) values, similar to the as-received substrates. These channels show record high electron mobility in the range of 196–85 cm 2 /V⋅s in unintentionally doped and Si-doped films in the doping range of 2 × 10 16 –1 × 10 20 cm −3 . Si delta-doped channels were also grown utilizing this substrate cleaning and the hybrid LT buffers. Record high electron Hall mobility of 110 cm 2 /V⋅s was measured for sheet charge density of 9.2 × 10 12 cm −2 . This substrate cleaning, combined with the LT buffer scheme, shows the potential of designing Si-doped β-Ga 2 O 3 channels with exceptional transport properties for high-performance Ga 2 O 3 -based electron devices.

Bhattacharyya, Arkka↗
NASA NTRS1989

Monolithic transistor gate energy recovery system

Energy is recovered from an insulated gate semiconductor switch, such as a MOSFET, that is otherwise lost in the gate capacitance by producing a notch in the gate control voltage for an interval B following an interval A after initial application of a gate control voltage pulse for turning the switch on, and a notch for an interval C following termination of the gate control voltage pulse followed by interval D during which the switch is turned on again, where each interval is a period .DELTA.T given by ##EQU1## L.sub.s is the inductance (discrete and/or parasitic) in series with the gate electrode of the insulated gate semiconductor switch, and C.sub.in is the capacitance of that switch between its gate and source electrodes. The interval .DELTA.T may be provided directly by timing in a pulse forming circuit for the gate control voltage applied, or adaptively by sensing the gate voltage v.sub.g and comparing it with fixed progressively higher voltages v.sub.1, v.sub.2 and v.sub.3, where v.sub.2 is intermediate v.sub.1 and v.sub.3 which correspond to the lower and upper levels of v.sub.g as the switch is turned off and on.

Rippel, Wally E.↗
NASA NTRS1988

Conversion Losses In GaAs Schottky-Barrier Diodes

Parasitic losses reduced with lightly doped epitaxial layers of proper thickness. Report presents calculations of conversion losses in Schottky-barrier diodes. Theoretical work directed toward reduction of parasitic losses through proper design of space-charge layers; possible, to reduce barrier capacitances and contributions to barrier resistances from undepleted epitaxial layers.

Von Roos, Oldwig↗
NASA NTRS1986

Conversion losses in GaAs Schottky-barrier diodes

The conversion losses of a Schottky-barrier diode have been calculated for a set of realistic diode parameters. It is found that previous work overestimated the substrate losses by 30 percent. It is also shown that a lightly doped epitaxial layer will decrease the barrier capacitance and with properly designed thickness will avoid any resistance losses due to this layer. Parasitic losses can thus be reduced substantially.

Von Roos, O.↗
DOE OSTI2024

Power Layout Design of a GaN HEMTs-Based High-Power High-Efficiency Three-Level ANPC Inverter for 800 V DC Bus System

Multiple commutation paths exist for switching devices in a three-level active neutral point clamped (3L-ANPC) inverter operation based on the selected switching state and current direction. In addition, the capacitive coupling path of the nonswitching device is a key design aspect for enabling high voltage and high current operation of gallium nitride (GaN) switches in 3L-ANPC topology. A comprehensive study of the switching transient events of inner, outer, and clamping devices of 3L-ANPC is presented in this article. The commutation mechanisms for worst-case transient voltage overshoots (TVOs) are identified. A simplified equivalent circuit model is presented to determine the design criteria for the power layout structure's parasitic inductances. A power layout strategy satisfying the design criteria is then proposed using an insulated metal substrate power printed circuit board (PCB) to enable efficient high-power operation. The proposed design minimizes the commutation and capacitive coupling path inductances to 6 nH and 11.5 nH, respectively. This enables the fast switching operation of GaN HEMTs at 800 V dc, 36 A with a low TVO of 31% verified through experimental three-level double pulse test results. Experimental evaluation of a three-phase 3L-ANPC hardware prototype based on the proposed power layout shows 99% efficiency at 800 V, 9.5 kVA and 50 kHz switching frequency. The proposed design achieves a low case-to-ambient thermal resistance of 2.3 °C/W.

42 ENGINEERING↗
NASA NTRS2012

Electrochemical Ultracapacitors Using Graphitic Nanostacks

Electrochemical ultracapacitors (ECs) have been developed using graphitic nanostacks as the electrode material. The advantages of this technology will be the reduction of device size due to superior power densities and relative powers compared to traditional activated carbon electrodes. External testing showed that these materials display reduced discharge response times compared to state-of-the-art materials. Such applications are advantageous for pulsed power applications such as burst communications (satellites, cell phones), electromechanical actuators, and battery load leveling in electric vehicles. These carbon nanostructures are highly conductive and offer an ordered mesopore network. These attributes will provide more complete electrolyte wetting, and faster release of stored charge compared to activated carbon. Electrochemical capacitor (EC) electrode materials were developed using commercially available nanomaterials and modifying them to exploit their energy storage properties. These materials would be an improvement over current ECs that employ activated carbon as the electrode material. Commercially available graphite nanofibers (GNFs) are used as precursor materials for the synthesis of graphitic nanostacks (GNSs). These materials offer much greater surface area than graphite flakes. Additionally, these materials offer a superior electrical conductivity and a greater average pore size compared to activated carbon electrodes. The state of the art in EC development uses activated carbon (AC) as the electrode material. AC has a high surface area, but its small average pore size inhibits electrolyte ingress/egress. Additionally, AC has a higher resistivity, which generates parasitic heating in high-power applications. This work focuses on fabricating EC from carbon that has a very different structure by increasing the surface area of the GNF by intercalation or exfoliation of the graphitic basal planes. Additionally, various functionalities to the GNS surface will be added that can exhibit pseudocapacitance. This pseudocapacitance exhibits faradaic (charge transfer) properties that can further increase the overall relative and volumetric capacitance of the material. A process is also proposed to use GNF as a precursor material to fabricate GNS that will be used as EC electrodes. This results in much better electrical conductivity than activated carbon. This is advantageous for high-pulsed-power applications to reduce parasitic heating. Larger average pore size allows more complete electrolyte wetting (faster charge transfer kinetics). These properties contribute to a lowered equivalent series resistance (ESR), increased specific power, shorter charging times, and decreased parasitic heating. The high density of basal plane edges provides nucleation sites for activation (addition of hydrophilic functional groups) that facilitate electrolyte wetting, and will contribute to pseudocapacitance.

Marotta, Christopher↗
DOE OSTI2022

β -Ga 2 O 3 MESFETs with insulating Mg-doped buffer grown by plasma-assisted molecular beam epitaxy

In this work, we develop in situ Mg doping techniques in plasma-assisted molecular beam epitaxy (PAMBE) of β -Ga 2 O 3 to compensate Si dopants at the substrate epilayer growth interface and eliminate parasitic leakage paths. Both abrupt and uniform Mg doping profiles over a wide range of concentrations were achieved in β -Ga 2 O 3 epilayers grown by PAMBE. Capacitance–voltage characteristics of Si and Mg co-doped samples confirmed the compensating effect of the Mg dopants. Mg delta-doping was then integrated into a β -Ga 2 O 3 metal-semiconductor field effect transistor structure and shown to be effective in eliminating source leakage. In conclusion, the results presented here show that Mg doping is a promising way to engineer insulating buffer layers for β -Ga 2 O 3 lateral devices grown by PAMBE.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRSDate not supplied

Impedance Matching a Quarter Wave Resonant Receiver to Improve Efficiency in Unipolar Capacitive Wireless Power Transfer

Impedance matching techniques to achieve high performance in conventional wireless power transfer (WPT) systems are well established. These WPT systems are modelled as a lumped circuit, where the voltages/currents are approximately uniform and mostly unaffected by parasitic elements. However, a group of WPT techniques exist that utilize parasitic elements to form a highly resonant power transfer condition at high quality factors, exploiting a distributed circuit operation that can be modeled as a mutually coupled transmission line. A calculated matching network typically becomes unmatched when connected to the transmission line, as it changes the electrical structure of the coupled transmission line. This is particularly true for WPT systems that use quarter wave (QWR) or half wave resonators (HWR) for the receiver. Here we present one technique of matching to a mutually coupled transmission line where a parallel path is formed that improves the power transfer efficiency without severely altering the transmission line characteristics.

Wireless↗