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State of randomly excited dynamical system estimated from noise measurements having finite duration, and optimal linear filter synthesized from conditional probability theory
A square root formulation is presented for the discrete combined state parameter estimation problem with linear plant dynamics, Gaussian random disturbances, and constant but uncertain parameters. The estimator is a combination of the classical Kalman filter and a maximum likelihood algorithm which maximizes the parameter log-likelihood function using a first order search routine.
Dynamic random-access-memory (RAM) data delay and storage unit developed to insure data received from satellite is stored and not lost when satellite is not within range of ground station. Stores 256K of serial data, with independent read and write capability.
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Scheme devised for asynchronous-message communication system for Mark III hypercube concurrent-processor network. Network consists of up to 1,024 processing elements connected electrically as though were at corners of 10-dimensional cube. Each node contains two Motorola 68020 processors along with Motorola 68881 floating-point processor utilizing up to 4 megabytes of shared dynamic random-access memory. Scheme intended to support applications requiring passage of both polled or solicited and unsolicited messages.
Error-correcting Hamming code built into circuit. A 256 K dynamic random-access memory (DRAM) circuit incorporates Hamming error-correcting code in its layout. Feature provides faster detection and correction of errors at less cost in amount of equipment, operating time, and software. On-chip error-correcting feature also makes new DRAM less susceptible to single-event upsets.
The spread of charge induced by an ion track in an integrated circuit and its subsequent collection at sensitive nodal junctions can cause multiple-bit errors. The authors have experimentally and analytically investigated this phenomenon using a 256-kb dynamic random-access memory (DRAM). The effects of different charge-transport mechanisms are illustrated, and two classes of ion-track multiple-bit error clusters are identified. It is demonstrated that ion tracks that hit a junction can affect the lateral spread of charge, depending on the nature of the pull-up load on the junction being hit. Ion tracks that do not hit a junction allow the nearly uninhibited lateral spread of charge.
Report describes experimental and computer-simulation study of multiple-bit errors caused by impingement of single energetic ions on 256-Kb dynamic random-access memory (DRAM) integrated circuit. Studies illustrate effects of different mechanisms for transport of charge from ion tracks to various elements of integrated circuits. Shows multiple-bit errors occur in two different types of clusters about ion tracks causing them.
A joint effort was undertaken on a Precision Segmented Reflector (PSR) Project. The missions in which the PSR is to be used will use large (up to 20 m in diameter) telescopes. The essential requirement for the telescopes is that the reflector surface of the primary mirror must be made extremely precise to allow no more than a few microns of errors and, additionally, this high surface precision must be maintained when the telescope is subjected to on-orbital mechanical and thermal disturbances. Based on the mass, size, and stability considerations, reflector surface formed by segmented, probably actively or passively controlled, composite panels are regarded as most suitable for future space based astronomical telescope applications. In addition to the design and fabrication of composite panels with a surface error of less than 3 microns RMS, PSR also develops related reflector structures, materials, control, and sensing technologies. As part of the planning effort for PSR Technology Demonstration, a system model which couples the reflector, consisting of panels, support truss and actuators, and the optical bench was assembled for dynamic simulations. Random vibration analyses using seismic data obtained from actual measurements at the test site designated for PSR Technology Demonstration are described.
Report presents results of experiments where multiple-bit errors were induced in 256-kbit commercial integrated-circuit dynamic random-access memory (DRAM) by variety of normally incident heavy ions. Idea demonstrates utility of DRAM and methods used to analyze experimental data, with view towards applying methods and data to other digital integrated circuits.
Experience with many spacecraft configurations boosted by a variety of launch vehicles indicates that the maximum loads experienced throughout most of the structure are inertial in origin. These loads arise from the dynamic elastic response of the flight vehicle to the transient disturbances of launch and flight, and are highly dependent on the dynamic characteristics of both the spacecraft and the launch vehicle. It has proved to be most advantageous, in the analysis of this critical dependency of loads upon vehicle dynamic properties, to establish a mathematical model in terms of normal mode characteristics. In this way, the vibration behavior of an elastomechanical structure (or substructure) can be described by means of the so-called modal or natural degrees of freedom. The conduct of a mode survey test and the use of a suitably test-verified model in loads analyses is essential to the flight worthiness certification process of space systems. The desirability of such tests is confirmed by the fact that, almost invariably, significant deficiencies in the analytical models are revealed by the results. Therefore, this experimental program was undertaken to determine those properties of a solid-propellant rocket motor (SRM) which are required to characterize a dynamic model. Random ambient-excited accelerations were measured at a series of stations along the motor for the purpose of identifying the motor beam-like stiffnesses in bending, shear, and torsion. From a system identification point of view, it is significant that stiffness properties of a subsystem (the motor) are determined from modes of the full system (motor/stand configuration) using mode shape data of the subsystem only. This contrasts with traditional system identification approaches which rely upon complete system mode shapes.
Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET
digital video camera system has been qualified for use in flight on the NASA supersonic F-15B Research Testbed aircraft. This system is capable of very-high-speed color digital imaging at flight speeds up to Mach 2. The components of this system have been ruggedized and shock-mounted in the aircraft to survive the severe pressure, temperature, and vibration of the flight environment. The system includes two synchronized camera subsystems installed in fuselage-mounted camera pods (see Figure 1). Each camera subsystem comprises a camera controller/recorder unit and a camera head. The two camera subsystems are synchronized by use of an MHub(TradeMark) synchronization unit. Each camera subsystem is capable of recording at a rate up to 10,000 pictures per second (pps). A state-of-the-art complementary metal oxide/semiconductor (CMOS) sensor in the camera head has a maximum resolution of 1,280 1,024 pixels at 1,000 pps. Exposure times of the electronic shutter of the camera range from 1/200,000 of a second to full open. The recorded images are captured in a dynamic random-access memory (DRAM) and can be downloaded directly to a personal computer or saved on a compact flash memory card. In addition to the high-rate recording of images, the system can display images in real time at 30 pps. Inter Range Instrumentation Group (IRIG) time code can be inserted into the individual camera controllers or into the M-Hub unit. The video data could also be used to obtain quantitative, three-dimensional trajectory information. The first use of this system was in support of the Space Shuttle Return to Flight effort. Data were needed to help in understanding how thermally insulating foam is shed from a space shuttle external fuel tank during launch. The cameras captured images of simulated external tank debris ejected from a fixture mounted under the centerline of the F-15B aircraft. Digital video was obtained at subsonic and supersonic flight conditions, including speeds up to Mach 2 and altitudes up to 50,000 ft (15.24 km). The digital video was used to determine the structural survivability of the debris in a real flight environment and quantify the aerodynamic trajectories of the debris.
This version of the SpaceCube will be a full-fledged, onboard space processing system capable of 2500+ MIPS, and featuring a number of plug-andplay gigabit and standard interfaces, all in a condensed 3x3x3 form factor [less than 10 watts and less than 3 lb (approximately equal to 1.4 kg)]. The main processing engine is the Xilinx SIRF radiation- hardened-by-design Virtex-5 FX-130T field-programmable gate array (FPGA). Even as the SpaceCube 2.0 version (currently under test) is being targeted as the platform of choice for a number of the upcoming Earth Science Decadal Survey missions, GSFC has been contacted by customers who wish to see a system that incorporates key features of the version 2.0 architecture in an even smaller form factor. In order to fulfill that need, the SpaceCube Mini is being designed, and will be a very compact and low-power system. A similar flight system with this combination of small size, low power, low cost, adaptability, and extremely high processing power does not otherwise exist, and the SpaceCube Mini will be of tremendous benefit to GSFC and its partners. The SpaceCube Mini will utilize space-grade components. The primary processing engine of the Mini is the Xilinx Virtex-5 SIRF FX-130T radiation-hardened-by-design FPGA for critical flight applications in high-radiation environments. The Mini can also be equipped with a commercial Xilinx Virtex-5 FPGA with integrated PowerPCs for a low-cost, high-power computing platform for use in the relatively radiation- benign LEOs (low-Earth orbits). In either case, this version of the Space-Cube will weigh less than 3 pounds (.1.4 kg), conform to the CubeSat form-factor (10x10x10 cm), and will be low power (less than 10 watts for typical applications). The SpaceCube Mini will have a radiation-hardened Aeroflex FPGA for configuring and scrubbing the Xilinx FPGA by utilizing the onboard FLASH memory to store the configuration files. The FLASH memory will also be used for storing algorithm and application code for the PowerPCs and the Xilinx FPGA. In addition, it will feature highspeed DDR SDRAM (double data rate synchronous dynamic random-access memory) to store the instructions and data of active applications. This version will also feature SATA-II and Gigabit Ethernet interfaces. Furthermore, there will also be general-purpose, multi-gigabit interfaces. In addition, the system will have dozens of transceivers that can support LVDS (low-voltage differential signaling), RS-422, or SpaceWire. The SpaceCube Mini includes an I/O card that can be customized to meet the needs of each mission. This version of the SpaceCube will be designed so that multiple Minis can be networked together using SpaceWire, Ethernet, or even a custom protocol. Scalability can be provided by networking multiple SpaceCube Minis together. Rigid-Flex technology is being targeted for the construction of the SpaceCube Mini, which will make the extremely compact and low-weight design feasible. The SpaceCube Mini is designed to fit in the compact CubeSat form factor, thus allowing deployment in a new class of missions that the previous SpaceCube versions were not suited for. At the time of this reporting, engineering units should be available in the summer 2012.
The Elpida EDS5104(08)ABTA 512Mb SDRAM is examined for programmatic impact of SEE. Use cases for the devices including EDAC and mode register reload are examined. Results indicate some SEE mitigation methods require careful application to achieve system-level benefits, while some event types are essentially mitigated by the application use. In the studied devices MBE and SEFI are identified and investigated as mechanisms requiring special consideration.
Advances in machine learning and deep neural networks has enabled complex engineering tasks like image recognition, anomaly detection, regression, and multi-objective optimization, to name but a few. The complexity of the algorithm architecture, e.g., the number of hidden layers in a deep neural network, typically grows with the complexity of the problems they are required to solve, leaving little room for interpreting (or explaining) the path that results in a specific solution. This drawback is particularly relevant for autonomous aerospace and aviation systems, where certifications require a complete understanding of the algorithm behavior in all possible scenarios. Including physics knowledge in such data-driven tools may improve the interpretability of the algorithms, thus enhancing model validation against events with low probability but relevant for system certification. Such events include, for example, spacecraft or aircraft sub-system failures, for which data may not be available in the training phase. This paper investigates a recent physics-informed learning algorithm for identification of system dynamics, and shows how the governing equations of a system can be extracted from data using sparse regression. The learned relationships can be utilized as a surrogate model which, unlike typical data-driven surrogate models, relies on the learned underlying dynamics of the system rather than large number of fitting parameters. The work shows that the algorithm can reconstruct the differential equations underlying the observed dynamics using a single trajectory when no uncertainty is involved. However, the training set size must increase when dealing with stochastic systems, e.g., nonlinear dynamics with random initial conditions.
The random vibration of the components of the space shuttle causing internal cargo bay acoustic impingement on the payload was investigated. The import factors to be considered in the design of acoustically loaded structures are the prediction of acoustic environment, prediction of structural response to this environment, and to determine the effect of the response on the structural strength requirements. Two basic responses were analyzed. The primary structure response due to random vibration is first analyzed. The output of primary structure response is used as an input to the secondary structure to calculate the component response.
The application of a sequential estimation algorithm, which compensates for random errors in the dynamic model, to the problem of estimating the state of a continuously thrusting solar electric propulsion space vehicle is investigated. The dynamic model errors, due to random anomalies in the propulsion system, are approximated successfully by both first order and second order Gauss-Markov processes to obtain a more accurate and stable orbit determination algorithm. The importance of correct dynamic and measurement modeling in achieving accurate estimates is demonstrated.