SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Impurity diffusion process produces precision silicon semiconductor junctions economically and fast. Oxide is deposited on a silicon wafer and a controlled concentration of impurity atoms in gaseous form is simultaneously introduced into the reaction.
Results of computer calculations using a one dimensional model of the silicon tandem junction solar cell with both front and back current collection are presented. Using realistically achievable geometrical and material parameters, the model predicts that with base widths of 50 micrometers and 100 micrometers and base resistivities between 1 ohm/cm and 20 ohm/cm, beginning of life efficiencies of 14% to 17% and end of life efficiencies of 12% to 14%, after about seven years in synchronous orbit, can be obtained.
Electron microscopy analysis of microinhomogeneities in commercial Si used in preparation of p-n junction devices
Large area GaAs/Ge cells offer substantial promise for increasing the power output from existing silicon solar array designs and for providing an enabled technology for missions hitherto impossible using silicon. Single junction GaAs/Ge cells offer substantial advantages in both size, weight, and cost compared to GaAs cells but the efficiency is limited to approximately 19.2 to 20 percent AMO. The thermal absorptance of GaAs/Ge cells is also worse than GaAs/GaAs cells (0.88 vs 0.81 typ.) due to the absorption in the Ge substrate. On the other hand dual junction GaAs/Ge cells offer efficiencies up to ultimately 24 percent AMO in sizes up to 8 x 8 cm but there are still technological issues remaining to achieve current matching in the GaAs and Ge cells. This can be achieved through tuned antireflection (AR) coatings, improved quality of the GaAs growth, improved quality Ge wafers and the use of a Back Surface Field (BSF)/Back Surface Reflector (BSR) in the Ge cell. Although the temperature coefficients of efficiency and voltage are higher for dual junction GaAs/Ge cells, it has been shown elsewhere that for typical 28 C cell efficiencies of 22 percent (dual junction) vs 18.5 percent (single junction) there is a positive power tradeoff up to temperatures as high as 120 C. Due to the potential ease of fabrication of GaAs/Ge dual junction cells there is likely to be only a small cost differential compared to single junction cells.
Effect of mechanical strain on electrical characteristics of germanium and silicon p-n junction devices
This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.
This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.
This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.
Piezojunction effect and silicon needle considered as sensory devices in accelerometers and transducers
Silicon solar cell with drift fields of various widths and magnitudes, considering performance changes before and after radiation
Micrometeroid damage of n-p silicon and CdS solar cells
Possible degradation effects produced in uncovered and covered N/P silicon solar cells by simulated micrometeoroid exposure
High energy proton irradiation and annealing of n and p type Si, comparing proton and electron damage
Use of small silicon diodes as radiation dosimeters in proton beams
Improving radiation resistance of silicon semiconductor junctions by doping with lithium
Photovoltaic laser to electric converters are attractive for use with a space-based laser power station. This paper presents the results of modeling studies for a silicon vertical junction converter used with a Nd laser. A computer code was developed for the model and this code was used to conduct a parametric study for a Si vertical junction converter consisting of one p-n junction irradiated with a Nd laser. These calculations predict an efficiency over 50 percent for an optimized converter.
Photovoltaic laser to electric converters are attractive for use with a space-based laser power station. The results of modeling studies for a silicon vertical junction converter used with a Nd laser are given. A computer code was developed for the model and this code was used to conduct a parametric study for a Si vertical junction converter consisting of one p-n junction irradiated with a Nd laser. These calculations predict an efficiency over 50 percent for an optimized converter.
Semiconductor power devices are typically rated for operation below 150 C. Little data is known for power semiconductors over 150 C. In most cases, the device is derated to zero operating power at 175 C. At the high temperature end of the temperature range, the intrinsic carrier concentration increases to equal the doping concentration level and the silicon behaves as an intrinsic semiconductor. The increase in intrinsic carrier concentration results in a shift of the Fermi level toward mid-bandgap at elevated temperatures. This produces a shift in devices characteristics as a function of temperature. By increasing the doping concentration higher operating temperatures can be achieved. This technique was used to fabricate low power analog and digital devices in silicon with junction operating temperatures in excess of 300 C. Additional temperature effects include increased p-n junction leakage with increasing temperature, resulting in increased resistivity. The temperature dependency of physical properties results in variations in device characteristics. These must be quantified and understood in order to develop extended temperature range operation.