SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Computer switching network consists of parallel and series combinations of mod 2 adders using the minimum number of gating levels. This network minimizes the propagation time in which a sequence of pseudonoise check bits are generated.
Pneumatic binary encoder replaces solenoid system in the pilot stage of a digital actuator. The encoder operates in flip-flop manner to valve gas at either high or low pressures. By rotating the disk in a pinion-to-encoding gear ratio, six to eight adder circuits may be operated from single encoder.
Digital array multiplier consisting of any number of identical digital adder cells in a repetitive planar configuration functions as a modular multiplier for use in computer applications of airborne vehicles. The modular multiplier utilizes large scale integration and metal oxide semiconductors.
Topological method uses the eye as pattern detector to trace path of transmission on truth table. Pathway selection is continually supervised by logician, allowing him to seek planar iterative solution desirable for fabrication of monolithic circuits. Method applies to parity generators, multiple output functions, full adders, and bit comparators.
The time- and frequency-domain properties of the orthogonal binomial sequences are presented. It is shown that these sequences, or digital filters based on them, can be generated using adders and delay elements only. The frequency-domain behavior of these nonrecursive binomial filters suggests a number of applications as low-pass Gaussian filters or as inexpensive bandpass filters.
Vector is divided into three variable sections, and each section is processed by unary-to-binary decoder or adder. Resulting network performs on iterative collection process; all outputs of same kind are collected in same manner. In combination with simple comparator gates, weighting network can also be used as majority network.
Telemetry (pulse code modulated) digital system usually sends binary numbers representing some parameter that is not value of binary number. Received binary number must be scaled and converted to binary coded decimal to operate readout device to display true value. Group of adders speed up binary number conversion and scaling in one operation.
A number of fundamentally ultra-reliable, all-magnetic logic circuits are developed using as a basis a single element ferrite structure wired as a logic delay element. By making minor additions or changes to the basic wiring pattern of the delay element other logic functions such as OR, AND, NEGATION, MAJORITY, EXCLUSIVE-OR, and FAN-OUT are developed. These logic functions are then used in the design of a full-adder, a set/reset flip-flop, and an edge detector. As a demonstration of the utility of all the developed devices, an 8-bit, all-magnetic, logic arithmetic unit capable of controlled addition, subtraction, and multiplication is designed. A new basic ferrite logic element and associated complementary logic scheme with the potential of improved performance is also described. Finally, an improved batch process for fabricating joint-free power drive and logic interconnect conductors for this basic class of all-magnetic logic is presented.
An input analog signal to be frequency analyzed is separated into N number of simultaneous analog signal components each identical to the original but delayed relative to the original by a successively larger time delay. The separated and delayed analog components are combined together in a suitable number of adders and attenuators in accordance with at least one component product of the continuous Fourier transform and analog signal matrices to separate the analog input signal into at least one of its continuous analog frequency components of bandwidth 1/N times the bandwidth of the original input signal. The original analog input signal can be reconstituted by combining the separate analog frequency components in accordance with the component products of the continuous Fourier transform and analog frequency component matrices. The continuous Fourier transformation is useful for spectrum analysis, filtering, transfer function synthesis, and communications.
Correlator can handle long-length pseudonoise sequences by adding shift registers, counters, and adders in "tree" configuration of basic 16-bit scheme. Correlation coefficient of unity or zero is generated when all bits of sequence are received and positioned correctly in input shift register.
The analog to digital converter stage derives a bit array of digital radiant energy signals representative of the amplitudes of an input radiant energy analog signal array and derives an output radiant energy analog signal array to serve as an input to succeeding stages. The converter stage includes a digital radiant energy array device which contains radiant energy array positions so that the analog array is less than a predetermined threshold level. A scaling device amplifies the radiant signal levels of the input array and the digital array so that the radiant energy signal level carried by the digital array corresponds to the threshold level. An adder device adds the signals of the scaled input and digital arrays at corresponding array positions to form the output analog array.
The use of the performance baseline from the flight planning manual as a reference to measure changes in cruise fuel flow rates was discussed. For the CF6-6D engine, the introduction of design changes for performance and durability reasons was seen to introduce an average increment relative to this baseline of 3.2% WFM increase at Nl, 2.5% Fn increase at Nl, 0.8% specific fuel consumption (SFC) increase at Fn, and 7 C EGT increase at Nl, while maintaining sufficient SFC margin of the delivered airplane. The effect of revenue service deterioration and performance restoration relative to the reference was shown to be an adder on top of these design effects. A schematic of typical CF6-6D performance through revenue service and airline maintenance is presented in terms of percent cruise SFC relative to an airline datum point (average level upon entering revenue service). The typical changes in SFC margin are shown for airline revenue service through for installations and refurbishments.
A method of concurrent error detection for arithmetic processors is described. Low-cost residue codes with check-length l and checkbase m = 2 to the l power - 1 are described for checking arithmetic operations of addition, subtraction, multiplication, division complement, shift, and rotate. Of the three number representations, the signed-magnitude representation is preferred for residue checking. Two methods of residue generation are described: the standard method of using modulo m adders and the method of using a self-testing residue tree. A simple single-bit parity-check code is described for checking the logical operations of XOR, OR, and AND, and also the arithmetic operations of complement, shift, and rotate. For checking complement, shift, and rotate, the single-bit parity-check code is simpler to implement than the residue codes.
It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.
Optical addition and storage units are described in this paper. These units are implemented using the Hughes Liquid Crystal Light Valve (LCLV) as a spatial light modulator using residue arithmetic for a numerical representation. The main hardware components of the design, besides the light valve, include an array of single-mode optical fibers that provide input information, a polarizing prism in combination with quarter-wave and half-wave retarders for residue arithmetic implementation in the adder, and a holographic array for spatial stability in the storage unit.
A 35 by 35 element pipelined convolutional kernel is being fabricated using VLSI chips, each containing a 5 by 1 segment of the kernel. Three levels of printed circuitry are used: the first level is used for the VLSI chips, the second level connects seven chips together on one platform, and the third level connects seven platforms with associated delay lines, all fitting on one board. Therefore, on each board there are seven rows of the kernel containing 245 multipliers and adders, and five such boards complete the kernel array. Each multiplier accepts an 8 bit picture element which is multiplied by a 16 bit weight. A truncated 22 bit product is added to a previously stored product sum and the results are shifted to the following multiplier as the next picture element is read in. The multiplier uses a modified Booth algorithm to reduce the number of shift add operations nearly in half. The filter box is presently configured as an ancillary box to a VAX 11/780, but can be connected to essentially any CPU. The I/O bandwidth is easily compatible with most CPU devices.
Basic elements of function generator are memory chips and interpolator chip, which incorporates multipliers and adders. Memory includes CMOS static random-access devices. 120 ns cycle time of devices allows real-time processing of image data.
The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.