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At least 73 records · Page 4

Enforcing constraints for time series prediction in supervised, unsupervised and reinforcement learning

We assume that we are given a time series of data from a dynamical system and our task is to learn the flow map of the dynamical system. We present a collection of results on how to enforce constraints coming from the dynamical system in order to accelerate the training of deep neural networks to represent the flow map of the system as well as increase their predictive ability. In particular, we provide ways to enforce constraints during training for all three major modes of learning, namely supervised, unsupervised and reinforcement learning. In general, the dynamic constraints need to include terms which are analogous to memory terms in model reduction formalisms. Such memory terms act as a restoring force which corrects the errors committed by the learned flow map during prediction. For supervised learning, the constraints are added to the objective function. For the case of unsupervised learning, in particular generative adversarial networks, the constraints are introduced by augmenting the input of the discriminator. Finally, for the case of reinforcement learning and in particular actor-critic methods, the constraints are added to the reward function. In addition, for the reinforcement learning case, we present a novel approach based on homotopy of the action-value function in order to stabilize and accelerate training. We use numerical results for the Lorenz system to illustrate the various constructions.

Stinis, Panagiotis↗

Low Power, Radiation Resilient Synchronous Edge Processing for Remote Monitoring

Next-generation space remote sensing systems may be equipped with imaging arrays that sense data at a rate that outstrips the processing capability of any computing hardware that can operate within a satellite’s power budget. This project developed novel convolutional and recurrent neural networks to detect and estimate point-like events amid clutter, and investigated their efficient and accurate implementation on analog in-memory computing systems that are 10-1000× more energy-efficient than digital processors. This project leveraged two memory devices at different levels of technological maturity: a large-scale analog computing prototype using commercial SONOS charge-trap memory, and electrochemical memory (ECRAM) with intrinsic radiation hardness. We experimentally demonstrated end-to-end analog processing of our neural networks on SONOS and characterized the radiation response of both SONOS and ECRAM. We advanced the state-of-the-art in ECRAM precision and reliability, and developed co-design methods to enable accurate long-term operation of SONOS analog accelerators in space radiation environments.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

RAM digital filter

Modification of conventional digital counting filter is designed to store all possible combinations of filter coefficients in random access memory. Filter includes analog-to-digital coverter, X shift register, memory, accumulator, and digital-to-analog converter.

Zohar, S.↗

Dual-ion ECRAM as a stable and accurate analog synapse

Electrochemical random-access memory (ECRAM) works by tuning the bulk electronic conductance of functional materials via reversible, electrochemical insertion of ions, resulting in stable analog resistive switching, attractive for analog in-memory and neuromorphic computing. However, achieving fast programming for training and long retention for inference has been elusive. Protonic ECRAM demonstrates fast programming but insufficient retention, while oxygen-based ECRAM with excellent retention requires elevated programming temperatures. Cu-based ECRAM offers a compromise, with an activation energy (E A ) of ≈0.76 eV between protons (E A ≈ 0.4 eV) and oxygen (E A > 1 eV), enabling extensive retention and room temperature programming. Combining Cu 2+ ions with protons to form a dual-ion ECRAM, we demonstrate two distinct switching behaviors: fast switching at ≤5 V, (E A ≈ 0.45 eV) via protons, and nonvolatile, room temperature switching at ≥8 V, with E A ≈ 0.76 eV via Cu 2+ ions. In conclusion, the Cu-based state exhibits a wide conductance range, with excellent retention, low noise, and linear current-voltage behavior, achieving digital-equivalent ImageNet inference accuracy.

analog in-memory computing↗

Electrical and structural properties of binary Ga–Sb phase change memory alloys

Material properties of Ga–Sb binary alloy thin films deposited under ultra-high vacuum conditions were studied for analog phase change memory (PCM) applications. Crystallization of this alloy was shown to occur in the temperature range of 180–264 °C, with activation energy >2.5 eV depending on the composition. X-ray diffraction (XRD) studies showed phase separation upon crystallization into two phases, Ga-doped A7 antimony and cubic zinc-blende GaSb. Synchrotron in situ XRD analysis revealed that crystallization into the A7 phase is accompanied by Ga out-diffusion from the grains. X-ray absorption fine structure studies of the local structure of these alloys demonstrated a bond length decrease with a stable coordination number of 4 upon amorphous-to-crystalline phase transformation. Mushroom cell structures built with Ga–Sb alloys on ø110 nm TiN heater show a phase change material resistance switching behavior with resistance ratio >100 under electrical pulse measurements. TEM and Energy Dispersive Spectroscopy (EDS) studies of the Ga–Sb cells after ∼100 switching cycles revealed that partial SET or intermediate resistance states are attained by the variation of the grain size of the material as well as the Ga content in the A7 phase. A mechanism for a reversible composition control is proposed for analog cell performance. These results indicate that Te-free Ga–Sb binary alloys are potential candidates for analog PCM applications.

Ume, Rubab (ORCID:0000000324766900)↗

CCD Memory

CCD memory device yields over 6.4 x 10 to the eighth power levels of information on single chip. Charge-coupled device (CCD) demonstrated to operate as either read-only-memory (ROM) or photon-programmable memory with capacity of 640,000 bits, with each bit capable of being weighted to more than 1,000 discrete analog levels. Larger memory capacities now possible using proposed approach in conjunction with CCD's now being fabricated, which yield over 4 x 10 to the ninth power discrete levels of information on single chip.

Janesick, James R.↗

When in-memory computing meets spiking neural networks—A perspective on device-circuit-system-and-algorithm co-design

This review explores the intersection of bio-plausible artificial intelligence in the form of spiking neural networks (SNNs) with the analog in-memory computing (IMC) domain, highlighting their collective potential for low-power edge computing environments. Through detailed investigation at the device, circuit, and system levels, we highlight the pivotal synergies between SNNs and IMC architectures. Additionally, we emphasize the critical need for comprehensive system-level analyses, considering the inter-dependencies among algorithms, devices, circuit, and system parameters, crucial for optimal performance. An in-depth analysis leads to the identification of key system-level bottlenecks arising from device limitations, which can be addressed using SNN-specific algorithm–hardware co-design techniques. This review underscores the imperative for holistic device to system design-space co-exploration, highlighting the critical aspects of hardware and algorithm research endeavors for low-power neuromorphic solutions.

Physics↗

An evaluation of the Intel 2920 digital signal processing integrated circuit

The circuit consists of a digital to analog converter, accumulator, read write memory and UV erasable read only memory. The circuit can convert an analog signal to a digital representation, perform mathematical operations on the digital signal and subsequently convert the digital signal to an analog output. Development software tailored for programming the 2920 is presented.

Heller, J.↗

Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

MacLeod, Todd C.↗

Design of a Multi-Level/Analog Ferroelectric Memory Device

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

MacLeod, Todd C.↗

The Ranicon - A resistive anode image converter

A versatile photon and charged particle imaging system is described. The Ranicon employs a microchannel electron multiplier plate to convert each detected event into a charge signal. This charge pulse is proximity-focused onto a large-area resistive anode plate equipped with pickup electrodes on its edges. Each event is located electronically by the ratios of the charges collected at the edges or by the differences of the signals' risetimes. One- or two-dimensional pictures are built up by storing events digitally (e.g., a core memory) or in analog form (e.g., a storage oscilloscope). Compact laboratory models have been constructed and tested. Operating characteristics, applications, limitations, and advantages of the Ranicon are discussed.

Lampton, M.↗

NASA Tech Briefs, April 2007

Topics include: Wearable Environmental and Physiological Sensing Unit; Broadband Phase Retrieval for Image-Based Wavefront Sensing; Filter Function for Wavefront Sensing Over a Field of View; Iterative-Transform Phase Retrieval Using Adaptive Diversity; Wavefront Sensing With Switched Lenses for Defocus Diversity; Smooth Phase Interpolated Keying; Maintaining Stability During a Conducted-Ripple EMC Test; Photodiode Preamplifier for Laser Ranging With Weak Signals; Advanced High-Definition Video Cameras; Circuit for Full Charging of Series Lithium-Ion Cells; Analog Nonvolatile Computer Memory Circuits; JavaGenes Molecular Evolution; World Wind 3D Earth Viewing; Lithium Dinitramide as an Additive in Lithium Power Cells; Accounting for Uncertainties in Strengths of SiC MEMS Parts; Ion-Conducting Organic/Inorganic Polymers; MoO3 Cathodes for High-Temperature Lithium Thin-Film Cells; Counterrotating-Shoulder Mechanism for Friction Stir Welding; Strain Gauges Indicate Differential-CTE-Induced Failures; Antibodies Against Three Forms of Urokinase; Understanding and Counteracting Fatigue in Flight Crews; Active Correction of Aberrations of Low-Quality Telescope Optics; Dual-Beam Atom Laser Driven by Spinor Dynamics; Rugged, Tunable Extended-Cavity Diode Laser; Balloon for Long-Duration, High-Altitude Flight at Venus; and Wide-Temperature-Range Integrated Operational Amplifier.

Source record↗

FPGA Flash Memory High Speed Data Acquisition

The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

Gonzalez, April↗

Development of a software interface for optical disk archival storage for a new life sciences flight experiments computer

The current Life Sciences Laboratory Equipment (LSLE) microcomputer for life sciences experiment data acquisition is now obsolete. Among the weaknesses of the current microcomputer are small memory size, relatively slow analog data sampling rates, and the lack of a bulk data storage device. While life science investigators normally prefer data to be transmitted to Earth as it is taken, this is not always possible. No down-link exists for experiments performed in the Shuttle middeck region. One important aspect of a replacement microcomputer is provision for in-flight storage of experimental data. The Write Once, Read Many (WORM) optical disk was studied because of its high storage density, data integrity, and the availability of a space-qualified unit. In keeping with the goals for a replacement microcomputer based upon commercially available components and standard interfaces, the system studied includes a Small Computer System Interface (SCSI) for interfacing the WORM drive. The system itself is designed around the STD bus, using readily available boards. Configurations examined were: (1) master processor board and slave processor board with the SCSI interface; (2) master processor with SCSI interface; (3) master processor with SCSI and Direct Memory Access (DMA); (4) master processor controlling a separate STD bus SCSI board; and (5) master processor controlling a separate STD bus SCSI board with DMA.

Bartram, Peter N.↗

High-Speed Ionic Synaptic Memory Based on 2D Titanium Carbide MXene

Synaptic devices with linear high-speed switching can accelerate learning in artificial neural networks (ANNs) embodied in hardware. Conventional resistive memories however suffer from high write noise and asymmetric conductance tuning, preventing parallel programming of ANN arrays. Electrochemical random-access memories (ECRAMs), where resistive switching occurs by ion insertion into a redox-active channel, aim to address these challenges due to their linear switching and low noise. ECRAMs using 2D materials and metal oxides however suffer from slow ion kinetics, whereas organic ECRAMs enable high-speed operation but face challenges toward on-chip integration due to poor temperature stability of polymers. Here, ECRAMs using 2D titanium carbide (Ti 3 C 2 T x ) MXene that combine the high speed of organics and the integration compatibility of inorganic materials in a single high-performance device are demonstrated. These ECRAMs combine the speed, linearity, write noise, switching energy, and endurance metrics essential for parallel acceleration of ANNs, and importantly, they are stable after heat treatment needed for back-end-of-line integration with Si electronics. The high speed and performance of these ECRAMs introduces MXenes, a large family of 2D carbides and nitrides with more than 30 stoichiometric compositions synthesized to date, as promising candidates for devices operating at the nexus of electrochemistry and electronics.

2D materials↗

Multi-speed multi-phase resolver converter

A multiphase converter circuit generates a plurality of sinusoidal outputs of displaced phase and given speed value from the output of an angular resolver system attachable to a motor excited by these multi-phase outputs, the resolver system having a lower speed value than that of the motor. The angular resolver system provides in parallel format sequential digital numbers indicative of the amount of rotation of the shaft of an angular position sensor associated with the angular resolver system. These numbers are used to excite simultaneously identical addresses of a plurality of addressable memory systems, each memory system having stored therein at sequential addresses sequential values of a sinusoidal wavetrain of a given number of sinusoids. The stored wavetrain values represent sinusoids displaced from each other in phase according to the number of output phases desired. A digital-to-analog converter associated with each memory system converts each accessed word to a corresponding analog value to generate attendant to rotation of the angular resolver a sinusoidal wave of proper phase at each of the plurality of outputs. By properly orienting the angular resolver system with respect to the rotor of the motor, essentially ripple-free torque is supplied to the rotor. The angular resolver system may employ an analog resolver feeding an integrated circuit resolver-to-digital converter to produce the requisite digital values serving as addresses. Alternative versions employing incremental or absolute encoders are also described.

Alhorn, Dean↗