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At least 73 records · Page 4

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NASA NTRS1972

Performance versus complexity of Viterbi and sequential decoding.

Performance versus complexity is compared for the Viterbi maximum likelihood decoder and the sequential decoder of convolutional codes for the additive white Gaussian noise memoryless channel. It is found that sequential decoders outperform Viterbi decoders at low data rates (less than 100 kbps) for the same complexity. However, Viterbi decoders are less complex than sequential decoders at high data rates (10 Mbps and greater) for the same performance.

Huth, G. K.↗

NASA NTRS1974

Method and apparatus for decoding compatible convolutional codes

This invention relates to learning decoders for decoding compatible convolutional codes. The decoder decodes signals which have been encoded by a convolutional coder and allows performance near the theoretical limit of performance for coded data systems. The decoder includes a sub-bit shift register wherein the received sub-bits are entered after regeneration and shifted in synchronization with a clock signal recovered from the received sub-bit stream. The received sub-bits are processed by a sub-bit decision circuit, entered into a sub-bit shift register, decoded by a decision circuit, entered into a data shift register, and updated to reduce data errors. The bit decision circuit utilizes stored sub-bits and stored data bits to determine subsequent data-bits. Data errors are reduced by using at least one up-date circuit.

Doland, G. D.↗

NASA NTRS1974

Buffer management for sequential decoding

Sequential decoding has been found to be an efficient means of communicating at low undetected error rates from deep space probes, but erasure or computational overflow remains a significant problem. Erasure of a block occurs when the decoder has not finished decoding that block at the time that it must be output. By drawing upon analogies in computer time sharing, this paper develops a buffer-management strategy which reduces the decoder idle time to a negligible level, and therefore improves the erasure probability of a sequential decoder. For a decoder with a speed advantage of ten and a buffer size of ten blocks, operating at an erasure rate of .01, use of this buffer-management strategy reduces the erasure rate to less than .0001.

Layland, J. W.↗

NASA NTRS1980

Viterbi/algebraic hybrid decoder

Decoder computer program is hybrid between optimal Viterbi and optimal algebraic decoders. Tests have shown that hybrid decoder outperforms any strictly Viterbi or strictly algebraic decoder and effectively handles compound channels. Algorithm developed uses syndrome-detecting logic to direct two decoders to assume decoding load alternately, depending on real-time channel characteristics.

Boyd, R. W.↗

NASA NTRS1983

Decoding: Codes and hardware implementation

The MST radars vary considerably from one installation to the next in the type of hardware, operating schedule and associated personnel. Most such systems do not have the computing power to decode in software when the decoding must be performed for each received pulse, as is required for certain sets of phase codes. These sets provide the best signal to sidelobe ratio when operating at the minimum band length allowed by the bandwidth of the transmitter. The development of the hardware phase decoder, and the applicability of each to decoding MST radar signals are discussed. A new design for a decoder which is very inexpensive to build, easy to add to an existing system and is capable of decoding on each received pulse using codes with a band length as short as one microsecond is presented.

Sulzer, M. P.↗

NASA NTRS1984

Error-trellis Syndrome Decoding Techniques for Convolutional Codes

An error-trellis syndrome decoding technique for convolutional codes is developed. This algorithm is then applied to the entire class of systematic convolutional codes and to the high-rate, Wyner-Ash convolutional codes. A special example of the one-error-correcting Wyner-Ash code, a rate 3/4 code, is treated. The error-trellis syndrome decoding method applied to this example shows in detail how much more efficient syndrome decoding is than Viterbi decoding if applied to the same problem. For standard Viterbi decoding, 64 states are required, whereas in the example only 7 states are needed. Also, within the 7 states required for decoding, many fewer transitions are needed between the states.

Reed, I. S.↗

NASA NTRS1987

High data rate Reed-Solomon encoding and decoding using VLSI technology

Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

Miller, Warner↗

NASA NTRS1989

Wiring Viterbi decoders (splitting deBruijn graphs)

A new Viterbi decoder, capable of decoding convolutional codes with constraint lengths up to 15, is under development for the Deep Space Network (DSN). A key feature of this decoder is a two-level partitioning of the Viterbi state diagram into identical subgraphs. The larger subgraphs correspond to circuit boards, while the smaller subgraphs correspond to Very Large Scale Integration (VLSI) chips. The full decoder is built from identical boards, which in turn are built from identical chips. The resulting system is modular and hierarchical. The decoder is easy to implement, test, and repair because it uses a single VLSI chip design and a single board design. The partitioning is completely general in the sense that an appropriate number of boards or chips may be wired together to implement a Viterbi decoder of any size greater than or equal to the size of the module.

Collins, O.↗

NASA NTRS1988

Decoding techniques for fine-fine geometry multi-anode microchannel arrays

The Multi-Anode Microchannel Array (MAMA) is a photon-counting detector which decodes the position of an event through coincidence discrimination. The decoding algorithm which associates a given event with the appropriate pixel is determined by the geometry of the array. The decoding process can be divided into two tasks: anode encoding and pixel decoding. Techniques for performing both tasks are described and contrasted in light of application requirements. Decode times of 75 nanoseconds have been achieved, and considerably faster decoders are possible given new architectures and technologies.

Kasle, David B.↗

NASA NTRS1991

Testing interconnected VLSI circuits in the Big Viterbi Decoder

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.↗

NASA NTRS1996

Good trellises for IC implementation of viterbi decoders for linear block codes

This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Moorthy, H. T.↗

NASA NTRS1996

Good trellises for IC implementation of viterbi decoders for linear block codes

Lin, Shu↗

NASA NTRS1997

Good Trellises for IC Implementation of Viterbi Decoders for Linear Block Codes

This paper investigates trellis structures of linear block codes for the integrated circuit (IC) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper-bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called add-compare-select (ACS)-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the very large scale integration (VISI) complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a nonminimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Moorthy, Hari T.↗

NASA NTRS2004

Milcom 04 Paper ID# 1158: A New Class of Turbo-like Codes with Efficient and Practical High-speed Decoders

Turbo codes not only achieve near Shannon-capacity performance, but also have decoders with modest complexity, which is crucial for implementation. So far efficient architectures for decoding of turbo codes have been proposed that is suitable for serial processing. In this paper a novel architecture for very high-speed turbo decoder is presented. The performance of this decoder is illustrated and the tradeoff between speed and efficiency is discussed. It is shown that some decoders can run faster by some order of magnitude while maintaining almost the same processing load.

interleaver design↗

DOE OSTI2019

Error Correction Decoding for Underwater Acoustic Tag Detection

This paper presents a decoding method applied to a set of underwater acoustic tags that employ very short signal beacons periodically transmitted. The tags use the CRC8- Dallas linear block code for error detection originally. Though the CRC8-Dallas is quite weak, syndrome-based error correction is applied to correct the decoding errors. Meanwhile, multi-channel array receivers are utilized to find the common decodes of the tag IDs, and the list of the true tag IDs is used to test the detection accuracy and false alarm rate. The proposed syndrome decoding method is applied to over 2 million files recorded in field experiments. The results demonstrate that the syndrome method yields around 9.85% more true positive decodes at the cost of a 2 - 5 times increase in false positive rates. Further insights are also gained to enable future improvement of the detection algorithms

Hall, Joseph↗

NASA NTRS1971

Viterbi decoding for satellite and space communication.

Convolutional coding and Viterbi decoding, along with binary phase-shift keyed modulation, is presented as an efficient system for reliable communication on power limited satellite and space channels. Performance results, obtained theoretically and through computer simulation, are given for optimum short constraint length codes for a range of code constraint lengths and code rates. System efficiency is compared for hard receiver quantization and 4 and 8 level soft quantization. The effects on performance of varying of certain parameters relevant to decoder complexity and cost are examined. Quantitative performance degradation due to imperfect carrier phase coherence is evaluated and compared to that of an uncoded system. As an example of decoder performance versus complexity, a recently implemented 2-Mbit/sec constraint length 7 Viterbi decoder is discussed. Finally a comparison is made between Viterbi and sequential decoding in terms of suitability to various system requirements.

Heller, J. A.↗

NASA NTRS1972

A very high speed hard decision sequential decoder.

Description of a 40-megabit-per-second hard decision sequential decoder which employs the fastest commercially available digital integrated circuits - MECL III. With this decoder an internal computational rate of 70,000,000 computations per second has been achieved. The computational efficiency of the decoding algorithm has been improved by incorporating two modifications to the Fano algorithm - namely, 'double quick threshold loosening' and 'diagonal steps.' On the basis of preliminary results, an output error rate of 0.00001 can be achieved with E sub b/N sub zero less than 5.4 dB at data rates up to 40 megabits per second. The very high internal operating speed of the decoder represents a factor of five increase in speed over any previous sequential decoder.

Gilhousen, K. S.↗

NASA NTRS1972

A very high speed hard decision sequential decoder.

Description of a 40-Mbps hard-decision sequential decoder for high-data-rate coding systems for earth-orbiting space missions with power-limited links. A prototype decoder has been designed and fabricated using the fastest commercially available digital integrated circuits, MECL III. Thus far, an internal computational rate of 70 million computations per second has been achieved. Computational efficiency of the decoding algorithm was greatly improved by incorporating two modifications to the Fano algorithm - 'double quick threshold loosening' and 'diagonal steps.' Preliminary results indicate that an output error rate of 0.00001 can be achieved with E sub b/N sub zero less than 5.4 dB at data rates up to 40 Mbps. At lower data rates, even less signal energy is required. This decoder is believed to be at least five times faster than any previous sequential decoder.

Gilhousen, K. S.↗